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LTC2241CUP-12-PBF

产品描述12-Bit, 210Msps ADC
文件大小583KB,共28页
制造商Linear ( ADI )
官网地址http://www.analog.com/cn/index.html
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LTC2241CUP-12-PBF概述

12-Bit, 210Msps ADC

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LTC2241-12
12-Bit, 210Msps ADC
FEATURES
DESCRIPTIO
Sample Rate: 210Msps
65.5dB SNR
78dB SFDR
1.2GHz Full Power Bandwidth S/H
Single 2.5V Supply
Low Power Dissipation: 585mW
LVDS, CMOS, or Demultiplexed CMOS Outputs
Selectable Input Ranges:
±0.5V
or
±1V
No Missing Codes
Optional Clock Duty Cycle Stabilizer
Shutdown and Nap Modes
Data Ready Output Clock
Pin Compatible Family
250Msps: LTC2242-12 (12-Bit), LTC2242-10 (10-Bit)
210Msps: LTC2241-12 (12-Bit), LTC2241-10 (10-Bit)
170Msps: LTC2240-12 (12-Bit), LTC2240-10 (10-Bit)
185Msps: LTC2220-1 (12-Bit)*
170Msps: LTC2220 (12-Bit), LTC2230 (10-Bit)*
135Msps: LTC2221 (12-Bit), LTC2231 (10-Bit)*
64-Pin 9mm
×
9mm QFN Package
The LTC
®
2241-12 is a 210Msps, sampling 12-bit A/D
converter designed for digitizing high frequency, wide
dynamic range signals. The LTC2241-12 is perfect for
demanding communications applications with AC perfor-
mance that includes 65.5dB SNR and 78dB SFDR. Ultralow
jitter of 95fs
RMS
allows IF undersampling with excellent
noise performance.
DC specs include
±0.7LSB
INL (typ),
±0.4LSB
DNL (typ)
and no missing codes over temperature.
The digital outputs can be either differential LVDS, or
single-ended CMOS. There are three format options for
the CMOS outputs: a single bus running at the full data rate
or two demultiplexed buses running at half data rate with
either interleaved or simultaneous update. A separate
output power supply allows the CMOS output swing to
range from 0.5V to 2.625V.
The ENC
+
and ENC
inputs may be driven differentially or
single ended with a sine wave, PECL, LVDS, TTL, or CMOS
inputs. An optional clock duty cycle stabilizer allows high
performance over a wide range of clock duty cycles.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
*LTC2220-1, LTC2220, LTC2221, LTC2230, LTC2231 are 3.3V parts.
APPLICATIO S
Wireless and Wired Broadband Communication
Cable Head-End Systems
Power Amplifier Linearization
Communications Test Equipment
TYPICAL APPLICATIO
REFH
REFL
FLEXIBLE
REFERENCE
2.5V
V
DD
0.5V
TO 2.625V
OV
DD
D11
D0
ANALOG
INPUT
INPUT
S/H
CORRECTION
LOGIC
OUTPUT
DRIVERS
CMOS
OR
LVDS
SFDR (dBFS)
+
12-BIT
PIPELINED
ADC CORE
OGND
CLOCK/DUTY
CYCLE
CONTROL
224112 TA01
ENCODE
INPUT
U
SFDR vs Input Frequency
85
80
75
70
65
60
1V RANGE
55
50
2V RANGE
45
40
0 100 200 300 400 500 600 700 800 900 1000
INPUT FREQUENCY (MHz)
224112 G11
U
U
224112fa
1

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