HIGH-SPEED
8K x 18 DUAL-PORT
STATIC RAM
Features
7035L
◆
◆
◆
◆
◆
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
– Commercial: 15ns (max.)
Low-power operation
– IDT7035L
Active: 800mW (typ.)
Standby: 1mW (typ.)
Separate upper-byte and lower-byte control for multiplexed
bus compatibility
IDT7035 easily expands data bus width to 36 bits or more
using the Master/Slave select when cascading more than
one device
◆
◆
◆
◆
◆
◆
◆
◆
◆
M/S = H for
BUSY
output flag on Master
M/S = L for
BUSY
input on Slave
Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
Battery backup operation—2V data retention
TTL-compatible, single 5V (±10%) power supply
Available in 100-pin Thin Quad Flatpack
Green parts available. See ordering information
Functional Block Diagram
R/
W
L
UB
L
R/
W
R
UB
R
LB
L
CE
L
OE
L
LB
R
CE
R
OE
R
I/O
9L
-I/O
17L
I/O
0L
-I/O
8L
BUSY
L
(1,2)
I/O
9R
-I/O
17R
I/O
Control
I/O
Control
I/O
0R
-I/O
8R
BUSY
R
(1,2)
A
12L
A
0L
Address
Decoder
13
MEMORY
ARRAY
13
Address
Decoder
A
12R
A
0R
CE
L
OE
L
R/
W
L
SEM
L
(2)
INT
L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
R
OE
R
R/
W
R
SEM
R
INT
R
(2)
4088 drw 01
M/
S
NOTES:
1. (MASTER):
BUSY
is output; (SLAVE):
BUSY
is input.
2.
BUSY
outputs and
INT
outputs are non-tri-stated push-pull.
JUNE 2019
1
DSC 4088/12
7035L
High-Speed 8K x 18 Dual-Port Static RAM
Commercial Temperature Range
Description
The IDT7035 is a high-speed 8K x 18 Dual-Port Static RAM. The
IDT7035 is designed to be used as a stand-alone 144K-bit Dual-Port RAM
or as a combination MASTER/SLAVE Dual-Port RAM for 36-bit or more
word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach
in 36-bit or wider memory system applications results in full-speed, error-
free operation without the need for additional discrete logic.
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature controlled by Chip Enable (CE) permits the on-chip circuitry of
each port to enter a very low standby power mode.
The IDT7035 utilizes a 18-bit wide data path to allow for parity at the
user's option. This feature is especially useful in data communications
applications where it is necessary to use a parity bit for transmission/
reception error checking.
Fabricated using CMOS high-performance technology, these de-
vices typically operate on only 800mW of power. Low-power (L) versions
offer battery backup data retention capability with typical power consump-
tion of 500µW from a 2V battery.
Pin Configurations
(1,2,3)
A
6L
A
7L
A
8L
A
9L
A
10L
A
11L
A
12L
LB
L
UB
L
CE
L
SEM
L
R/W
L
V
CC
OE
L
I/O
0L
I/O
1L
GND
I/O
2L
I/O
3L
I/O
4L
I/O
5L
I/O
6L
I/O
7L
I/O
9L
I/O
10L
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
50
76
49
77
78
48
79
47
80
46
81
45
44
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
1 2 3 4 5 6
43
42
41
40
39
N/C
N/C
N/C
N/C
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
INT
L
BUSY
L
GND
M/S
BUSY
R
INT
R
A
0R
A
1R
A
2R
A
3R
A
4R
N/C
N/C
N/C
N/C
7035
PNG100
(4)
100-Pin TQFP
Top View
38
37
36
35
34
33
32
31
30
29
28
27
26
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
A
5R
A
6R
A
7R
A
8R
A
9R
A
10R
A
11R
A
12R
LB
R
UB
R
CE
R
SEM
R
GND
R/W
R
OE
R
I/O
16R
GND
I/O
15R
I/O
14R
I/O
13R
I/O
12R
I/O
11R
I/O
10R
I/O
9R
I/O
7R
4088 drw 02
NOTES:
1. All V
CC
pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
N/C
N/C
I/O
8L
I/O
17L
I/O
11L
I/O
12L
I/O
13L
I/O
14L
GND
I/O
15L
I/O
16L
V
CC
GND
I/O
0R
I/O
1R
I/O
2R
V
CC
I/O
3R
I/O
4R
I/O
5R
I/O
6R
I/O
8R
I/O
17R
N/C
N/C
6.42
2
7035L
High-Speed 8K x 18 Dual-Port Static RAM
Industrial and
Commercial Temperature Range
Pin Names
Left Port
CE
L
R/W
L
OE
L
A
0L
- A
12L
I/O
0L
- I/O
17L
SEM
L
UB
L
LB
L
INT
L
BUSY
L
CE
R
R/W
R
OE
R
A
0R
- A
12R
I/O
0R
- I/O
17R
SEM
R
UB
R
LB
R
INT
R
BUSY
R
M/S
V
CC
GND
Right Port
Chip Enable
Read/Write Enable
Output Enable
Address
Data Input/Output
Semaphore Enable
Upper Byte Select
Lower Byte Select
Interrupt Flag
Busy Flag
Master or Slave Select
Power
Ground
4088 tbl 01
Names
Truth Table I: Non-Contention Read/Write Control
Inputs
(1)
CE
H
X
L
L
L
L
L
L
X
NOTE:
Outputs
UB
X
H
L
H
L
L
H
L
X
LB
X
H
H
L
L
H
L
L
X
SEM
H
H
H
H
H
H
H
H
X
I/O
9-17
High-Z
High-Z
DATA
IN
High-Z
DATA
IN
DATA
OUT
High-Z
DATA
OUT
High-Z
I/O
0-8
High-Z
High-Z
High-Z
DATA
IN
DATA
IN
High-Z
DATA
OUT
DATA
OUT
High-Z
Mode
Deselected: Power-Down
Both Bytes Deselected
Write to Upper Byte Only
Write to Lower Byte Only
Write to Both Bytes
Read Upper Byte Only
Read Lower Byte Only
Read Both Bytes
Outputs Disabled
4088 tbl 02
R/W
X
X
L
L
L
H
H
H
X
OE
X
X
X
X
X
L
L
L
H
1. A
0L
— A
12L
≠
A
0R
— A
12R
3
6.42
7035L
High-Speed 8K x 18 Dual-Port Static RAM
Commercial Temperature Range
Truth Table II: Semaphore Read/Write Control
(1)
Inputs
CE
H
X
H
X
L
L
R/W
H
H
OE
L
L
X
X
X
X
UB
X
H
X
H
L
X
LB
X
H
X
H
X
L
SEM
L
L
L
L
L
L
I/O
9-17
DATA
OUT
DATA
OUT
DATA
IN
DATA
IN
______
______
Outputs
I/O
0-8
DATA
OUT
DATA
OUT
DATA
IN
DATA
IN
______
______
Mode
Read Data in Semaphore Flag
Read Data in Semaphore Flag
Write I/O
0
into Semaphore Flag
Write I/O
0
into Semaphore Flag
Not Allowed
Not Allowed
4088 tbl 03
↑
↑
X
X
NOTE:
1. There are eight semaphore flags written to via I/O
0
and read from I/O
0
- I/O
17.
These eight semaphores are addressed by A
0
- A
2
.
Absolute Maximum Ratings
(1)
Symbol
V
TERM
(2)
Rating
Terminal Voltage
with Respect
to GND
Temperature
Under Bias
Storage
Temperature
DC Output
Current
Commercial
& Industrial
-0.5 to +7.0
Unit
V
Maximum Operating
Temperature and Supply Voltage
(1)
Grade
Commercial
Ambient
Temperature
0
O
C to +70
O
C
-40
O
C to +85
O
C
GND
0V
0V
Vcc
5.0V
+
10%
5.0V
+
10%
4088 tbl 05
T
BIAS
T
STG
I
OUT
-55 to +125
-65 to +150
50
o
C
C
Industrial
o
NOTES:
1. This is the parameter T
A
. This is the "instant on" case temperature.
mA
4088 tbl 04
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
2. V
TERM
must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20 mA for the period over V
TERM
> Vcc + 10%.
Recommended DC Operating
Conditions
Symbol
V
CC
GND
V
IH
V
IL
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
4.5
0
2.2
-0.5
(1)
Typ.
5.0
0
____
____
Max.
5.5
0
6.0
(2)
0.8
Unit
V
V
V
V
4088 tbl 06
Capacitance
(T
A
= +25°C, f = 1.0MHz)
(1)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output
Capacitance
Conditions
(2)
V
IN
= 3dV
V
OUT
= 3dV
Max.
9
10
Unit
pF
pF
4088 tbl 07
NOTES:
1. V
IL
> -1.5V for pulse width less than 10ns.
2. V
TERM
must not exceed Vcc + 10%.
NOTES:
1. This parameter is determined by device characterization but is not production
tested. For TQFP Package Only.
2. 3dV references the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.
6.42
4
7035L
High-Speed 8K x 18 Dual-Port Static RAM
Industrial and
Commercial Temperature Range
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(V
CC
= 5.0V ± 10%)
7035S
Symbol
|I
LI
|
|I
LO
|
V
OL
V
OH
Parameter
Input Leakage Current
(1)
Output Leakage Current
Output Low Voltage
Output High Voltage
Test Conditions
V
CC
= 5.5V, V
IN
= 0V to V
CC
CE
= V
IH
, V
OUT
= 0V to V
CC
I
OL
= 4mA
I
OH
= -4mA
Min.
___
___
___
7035L
Max.
10
10
0.4
___
Min.
___
___
___
Max.
5
5
0.4
___
Unit
µA
µA
V
V
4088 tbl 08
2.4
2.4
NOTE:
1. At Vcc < 2.0V input leakages are undefined.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(1)
(V
CC
= 5.0V ± 10%)
Symbol
I
CC
Parameter
Dynamic Operating Current
(Both Ports Active)
Test Condition
CE
= V
IL
, Outputs Disabled
SEM
= V
IH
f = f
MAX
(3)
Version
COM'L
IND
COM'L
IND
COM'L
S
L
S
L
S
L
S
L
S
L
S
L
S
L
S
L
S
L
S
L
7035X15
Com'l Only
Typ.
(2)
Max.
170
170
____
____
7035X20
Com'l & Ind
Typ.
(2)
Max.
160
160
160
160
20
20
20
20
95
95
95
95
1.0
0.2
1.0
0.2
90
90
90
90
290
240
370
320
60
50
90
70
180
150
240
210
15
5
30
10
155
130
225
200
Unit
mA
310
260
____
____
I
SB1
Standby Current
(Both Ports - TTL Level
Inputs)
CE
L
=
CE
R
= V
IH
SEM
R
=
SEM
L
= V
IH
f = f
MAX
(3)
20
20
____
____
60
50
____
____
mA
I
SB2
Standby Current
(One Port - TTL Level Inputs)
CE
"A"
= V
IL
and
CE
"B"
= V
IH
(5)
Active Port Outputs Disabled,
f=f
MAX
(3)
SEM
R
=
SEM
L
= V
IH
105
105
____
____
190
160
____
____
mA
IND
COM'L
IND
COM'L
IND
I
SB3
Full Standby Current (Both
Ports - All CMOS Level
Inputs)
Both Ports
CE
L
and
CE
R
> V
CC
- 0.2V
V
IN
> V
CC
- 0.2V or
V
IN
< 0.2V, f = 0
(4)
SEM
R
=
SEM
L
> V
CC
- 0.2V
CE
"A"
< 0.2V and
CE
"B"
> V
CC
- 0.2V
(5)
SEM
R
=
SEM
L
> V
CC
- 0.2V
V
IN
> V
CC
- 0.2V or V
IN
< 0.2V
Active Port Outputs Disabled
f = f
MAX
(3)
1.0
0.2
____
____
15
5
____
____
mA
I
SB4
Full Standby Current
(One Port - All CMOS Level
Inputs)
100
100
____
____
170
140
____
____
mA
NOTES:
1. 'X' in part numbers indicates power rating (S or L)
2. V
CC
= 5V, T
A
= +25°C, and are not production tested. Icc dc
=
120mA (TYP)
3. At f = f
MAX
,
address and I/O'
S
are cycling at the maximum frequency read cycle of 1/t
RC
, and using “AC Test Conditions” of input levels of
GND to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4088 tbl 09
5
6.42
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