HY29DL162/HY29DL163
16 Megabit (2M x 8/1M x16) Low Voltage,
Dual Bank, Simultaneous Read/Write Flash Memory
KEY FEATURES
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Single Power Supply Operation
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Read, program, and erase operations
from 2.7 to 3.6 V
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Ideal for battery-powered applications
Simultaneous Read/Write Operations
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Host system can program or erase in one
bank while simultaneously reading from any
sector in the other bank with zero latency
between read and write operations
High Performance
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70 and 80 ns access time versions with
30pF load
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90 and 120 ns access time versions with
100pF load
Ultra Low Power Consumption (Typical
Values)
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Automatic sleep mode current: 200 nA
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Standby mode current: 200 nA
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Read current: 10 mA (at 5 MHz)
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Program/erase current: 15 mA
Boot-Block Sector Architecture with 39
Sectors in Two Banks for Fast In-System
Code Changes
Secured Sector: An Extra 64 Kbyte Sector
that Can Be:
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Factory locked and identifiable: 16 bytes
available for a secure, random factory-
programmed Electronic Serial Number
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Customer lockable: Can be read, program-
med, or erased just like other sectors
Flexible Sector Architecture
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Sector Protection allows locking of a
sector or sectors to prevent program or
erase operations within that sector
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Temporary Sector Unprotect allows
changes in locked sectors (requires high
voltage on RESET# pin)
Automatic Erase Algorithm Erases Any
Combination of Sectors or the Entire Chip
Automatic Program Algorithm Writes and
Verifies Data at Specified Addresses
Compliant with Common Flash Memory
Interface (CFI) Specification
Minimum 100,000 Write Cycles per Sector
(1,000,000 cycles Typical)
Compatible with JEDEC Standards
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Pinout and software compatible with
single-power supply Flash devices
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Superior inadvertent write protection
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Data# Polling and Toggle Bits
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Provide software confirmation of completion
of program or erase operations
Ready/Busy# Pin
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Provides hardware confirmation of
completion of program or erase operations
Erase Suspend
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Suspends an erase operation to allow
programming data to or reading data from
a sector in the same bank
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Erase Resume can then be invoked to
complete the suspended erasure
Hardware Reset Pin (RESET#) Resets the
Device to Reading Array Data
WP#/ACC Input Pin
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Write protect (WP#) function allows
hardware protection of two outermost boot
sectors, regardless of sector protect status
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Acceleration (ACC) function provides
accelerated program times
Fast Program and Erase Times
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Sector erase time: 0.5 sec typical
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Byte/Word program time utilizing
Acceleration function: 10 µs typical
Space Efficient Packaging
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48-pin TSOP and 48-ball FBGA packages
LOGIC DIAGRAM
20
A[19:0]
DQ[7:0]
7
CE#
OE#
WE#
RESET#
BYTE#
DQ[14:8]
DQ[15]/A[-1]
WP#/ACC
RY/BY#
8
Preliminary
Revision 1.3, June 2001
HY29DL162/HY29DL163
GENERAL DESCRIPTION
The HY29DL162/HY29DL163 (HY29DL16x) is a
16 Mbit, 3 volt-only CMOS Flash memory orga-
nized as 2,097,152 (2M) bytes or 1,048,576 (1M)
words. The device is available in 48-pin TSOP
and 48-ball FBGA packages. Word-wide data
(x16) appears on DQ[15:0] and byte-wide (x8) data
appears on DQ[7:0].
The HY29DL16x Flash memory array is organized
into 39 sectors in two banks. Bank 1 contains
eight 8 Kbyte boot/parameter sectors and 3 or 7
larger sectors of 64 Kbytes each, depending on
the version of the device. Bank 2 contains the
rest of the memory array, organized as 28 or 24
sectors of 64 Kbytes:
Bank 1
HY29DL162
HY29DL163
8 x 8KB/4KW
3 x 64KB/32KW
8 x 8KB/4KW
7 x 64KB/32KW
Bank 2
28 x 64KB/32KW
24 x 64KB/32KW
Device programming is performed a byte/word at
a time by executing the four-cycle Program Com-
mand write sequence. This initiates an internal
algorithm that automatically times the program
pulse widths and verifies proper cell margin. Faster
programming times can be achieved by placing
the HY29DL16x in the Unlock Bypass mode, which
requires only two write cycles to program data in-
stead of four.
The HY29DL16x’s sector erase architecture allows
any number of array sectors, in one or both banks,
to be erased and reprogrammed without affecting
the data contents of other sectors. Device erasure
is initiated by executing the Erase Command se-
quence. This initiates an internal algorithm that
automatically preprograms the sector before ex-
ecuting the erase operation. As during program-
ming cycles, the device automatically times the
erase pulse widths and verifies proper cell mar-
gin. Hardware Sector Group Protection option-
ally disables both program and erase operations
in any combination of the sector groups, while
Temporary Sector Group Unprotect, which re-
quires a high voltage on one pin, allows in-system
erasure and code changes in previously protected
sector groups. Erase Suspend enables the user
to put erase on hold in a bank for any period of
time to read data from or program data to any
sector in that bank that is not selected for era-
sure. True background erase can thus be
achieved. Because the HY29DL16x features si-
multaneous read/write capability, there is no need
to suspend to read from a sector located within a
bank that does not contain sectors marked for era-
sure. The device is fully erased when shipped
from the factory.
Addresses and data needed for the programming
and erase operations are internally latched during
write cycles. The host system can detect comple-
tion of a program or erase operation by observing
the RY/BY# pin or by reading the DQ[7] (Data#
Polling) and DQ[6] (Toggle) status bits. Hardware
data protection measures include a low V
CC
de-
tector that automatically inhibits write operations
during power transitions.
After a program or erase cycle has been com-
pleted, or after assertion of the RESET# pin (which
terminates any operation in progress), the device
is ready to read data or to accept another com-
r1.3/June 01
The device features simultaneous read/write op-
eration which allows the host system to invoke a
program or erase operation in one bank and im-
mediately and simultaneously read data from the
other bank, except if that bank has any sectors
marked for erasure, with zero latency. This re-
leases the system from waiting for the completion
of program or erase operations, thus improving
overall system performance.
The HY29DL16x can be programmed and erased
in-system with a single 2.7 - 3.6 volt V
CC
supply.
Internally generated and regulated voltages are
provided for program and erase operations, so that
the device does not require a higher voltage V
PP
power supply to perform those functions. The de-
vice can also be programmed in standard EPROM
programmers. Access times as low as 70 ns are
offered for timing compatibility with the zero wait
state requirements of high speed microproces-
sors. To eliminate bus contention, the HY29DL16x
has separate chip enable (CE#), write enable
(WE#) and output enable (OE#) controls.
The device is compatible with the JEDEC single-
power-supply Flash command set standard. Com-
mands are written to the command register using
standard microprocessor write timings, from where
they are routed to an internal state-machine that
controls the erase and programming circuits.
2
HY29DL162/HY29DL163
mand. Reading data out of the device is similar to
reading from other Flash or EPROM devices.
The Secured Sector is an extra 64 Kbyte sector
capable of being permanently locked at the fac-
tory or by customers. The Secured Indicator Bit
(accessed via the Electronic ID mode) is perma-
nently set to a 1 if the part is factory locked, and
permanently set to a 0 if customer lockable. This
way, customer lockable parts can never be used
to replace a factory locked part. Factory locked
parts provide several options. The Secured Sec-
tor may store a secure, random 16-byte ESN (Elec-
tronic Serial Number), customer code programmed
at the factory, or both. Customer Lockable parts
may utilize the Secured Sector as bonus space,
reading and writing like any other Flash sector, or
may permanently lock their own code there.
The WP#/ACC pin provides access to two func-
tions. The Write Protect function provides a hard-
ware method of protecting certain boot sectors
without using a high voltage. The Accelerate func-
tion speeds up programming operations, and is
intended primarily to allow faster manufacturing
throughput.
BLOCK DIAGRAM
DQ[15:0]
Two power-saving features are embodied in the
HY29DL16x. When addresses have been stable
for a specified amount of time, the device enters
the automatic sleep mode. The host can also place
the device into the standby mode. Power con-
sumption is greatly reduced in both these modes.
Common Flash Memory Interface (CFI)
To make Flash memories interchangeable and to
encourage adoption of new Flash technologies,
major Flash memory suppliers developed a flex-
ible method of identifying Flash memory sizes and
configurations in which all necessary Flash device
parameters are stored directly on the device.
Parameters stored include memory size, byte/word
configuration, sector configuration, necessary volt-
ages and timing information. This allows one set
of software drivers to identify and use a variety of
different, current and future Flash products. The
standard which details the software interface nec-
essary to access the device to identify it and to
determine its characteristics is the Common Flash
Memory Interface (CFI) Specification. The
HY29DL16x is fully compliant with this specification.
A[19:0], A[-1]
STATE
CONTROL
COMMAND
REGISTER
ERASE VOLTAGE
GENERATOR AND
SECTOR SWITCHES
CFI DATA
MEMORY
PROGRAM
VOLTAGE
GENERATOR
Y-DECODER
I/O CONTROL
I/O BUFFERS
WE#
CE#
OE#
RESET#
BYTE#
RY/BY#
WP#/ACC
CFI
CONTROL
DATA LATCH
ADDRESS LATCH
Y-GATING
16 Mb FLASH
MEMORY
ARRAY
(2 Banks,
39 Sectors)
TIMER
A[19:0], A[-1]
X-DECODER
V
CC
DETECTOR
0.5 Mb FLASH
Security Sector
r1.3/June 01
3
HY29DL162/HY29DL163
PIN CONFIGURATIONS
A[15]
A[14]
A[13]
A[12]
A[11]
A[10]
A[9]
A[8]
A[19]
NC
WE#
RESET#
NC
WP#/ACC
RY/BY#
A[18]
A[17]
A[7]
A[6]
A[5]
A[4]
A[3]
A[2]
A[1]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A[16]
BYTE#
V
SS
DQ[15]/A[-1]
DQ[7]
DQ[14]
DQ[6]
DQ[13]
DQ[5]
DQ[12]
DQ[4]
V
CC
DQ[11]
DQ[3]
DQ[10]
DQ[2]
DQ[9]
DQ[1]
DQ[8]
DQ[0]
OE#
V
SS
CE#
A[0]
TSOP48
48-Ball FBGA (Top View, Balls Facing Down)
A6
A[13]
B6
A[12]
C6
A[14]
D6
A[15]
E6
A[16]
F6
BYTE#
G6
DQ[15]/A[-1]
H6
V
SS
A5
A[9]
B5
A[8]
C5
A[10]
D5
A[11]
E5
DQ[7]
F5
DQ[14]
G5
DQ[13]
H5
DQ[6]
A4
WE#
B4
RESET#
C4
NC
D4
A[19]
E4
DQ[5]
F4
DQ[12]
G4
V
CC
H4
DQ[4]
A3
RY/BY#
B3
WP#/ACC
C3
A[18]
D3
NC
E3
DQ[2]
F3
DQ[10]
G3
DQ[11]
H3
DQ[3]
A2
A[7]
B2
A[17]
C2
A[6]
D2
A[5]
E2
DQ[0]
F2
DQ[8]
G2
DQ[9]
H2
DQ[1]
A1
A[3]
B1
A[4]
C1
A[2]
D1
A[1]
E1
A[0]
F1
CE#
G1
OE#
H1
V
SS
4
r1.3/June 01
HY29DL162/HY29DL163
SIGNAL DESCRIPTIONS
Name
A[19:0]
Type
Inputs
Description
Address, active High.
In word mode, these 20 inputs select one of 1,048,576
(1M) words within the array for read or write operations. In byte mode, these
inputs are combined with the DQ[15]/A[-1] input (LSB) to select one of 2,097,152
(2M) bytes within the array for read or write operations.
DQ[15]/A[-1],
DQ[14:0]
BY TE#
CE#
Data Bus, active High
. In word mode, these pins provide a 16-bit data path
Inputs/Outputs for read and write operations. In byte mode, DQ[7:0] provide an 8-bit data path
Tri-state
and DQ[15]/A[-1] is used as the LSB of the 21-bit byte address input. DQ[14:8]
are unused and remain tri-stated in byte mode.
Input
Input
Byte Mode, active Low.
Controls the Byte/Word configuration of the device.
Low selects Byte mode, High selects Word mode.
Chip Enable, active Low.
This input must be asserted to read data from or
write data to the HY 29DL16x. When High, the data bus is tri-stated and the
device is placed in the Standby mode.
Output Enable, active Low
. This input must be asserted for read operations
and negated for write operations. BY TE# determines whether a byte or a word
is read during the read operation. When High, data outputs from the device are
disabled and the data bus pins are placed in the high impedance state.
Write Enable, active Low.
Controls writing of command sequences in order to
program data or erase sectors of the memory array. A write operation takes
place w hen WE# is asser t ed w hile CE# is Low and O E# is High. BY TE#
determines whether a byte or a word is written during the write operation.
Hardware Reset, active Low.
Provides a hardware method of resetting the
HY 29DL16x to the read array state. When the device is reset, it immediately
terminates any operation in progress. The data bus is tri-stated and all read/write
commands are ignored while the input is asserted. While RESET# is asserted,
the device will be in the Standby mode.
Re a dy / Bus y St a t us .
I nd ic a t e s w he t he r a w r it e o r e r a s e c o mma nd is in
progress or has been completed. Valid after the rising edge of the final WE#
pulse of a command sequence. I t remains Low w hile t he device is act ively
programming data or erasing, and goes High when it is ready to read array data.
Write Protect, active Low/Accelerate (V
HH
).
Wr it e Pr ot ect Funct ion: Placing t his pin at V
IL
disables pr ogr am and er ase
oper at ions in t w o of t he eight 8 Kbyt e/ 4 Kw or d boot sect or s. The af f ect ed
sectors are S0 and S1 in a bottom-boot device, or S37 and S38 in a top-boot
device. If the pin is placed at V
IH
, the protection state of those tw o sectors
reverts to whether they were last set to be protected or unprotected using the
method described in the Sector Group Protection and Unprotection sections.
Accelerate Function: If V
HH
is applied to this input, the device enters the Unlock
Bypass mode, t empor ar ily unpr ot ect s any pr ot ect ed sect or s, and uses t he
higher voltage on the pin to reduce the time required for program operations.
The syst em w ould t hen use t he t w o- cycle pr ogr am command sequence as
required by the Unlock Bypass mode. Removing V
HH
from the pin returns the
device to normal operation.
This pin must not be at V
HH
for operations other than accelerated programming,
or devic e damage may r es ult . Leaving t he pin unc onnec t ed may r es ult in
inconsistent device operation.
3-volt (nominal) power supply.
Power and signal ground.
OE#
Input
WE#
Input
RESET#
Input
RY /BY #
Output
Open Drain
WP#/ACC
Input
V
CC
V
SS
r1.3/June 01
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