Data Sheet
June 2007
TruePHY
™
ET1011C
Gigabit Ethernet Transceiver
Features
■
Introduction
The LSI ET1011C is a Gigabit Ethernet transceiver
fabricated on a single CMOS chip. Packaged in
either an 128-pin TQFP, an 84-pin MLCC, or a
68-pin MLCC, the ET1011C is built on 0.13 µm tech-
nology for low power consumption and application in
server and desktop NIC cards. It features single
power supply operation using on-chip regulator con-
trollers. The 10/100/1000Base-T device is fully com-
pliant with
IEEE
®
802.3, 802.3u, and 802.3ab
standards.
The ET1011C uses an oversampling architecture to
gather more signal energy from the communication
channel than possible with traditional architectures.
The additional signal energy or analog complexity
transfers into the digital domain. The result is an ana-
log front end that delivers robust operation, reduced
cost, and lower power consumption than traditional
architectures.
Using oversampling has allowed for the implementa-
tion of a fractionally spaced equalizer, which provides
better equalization and has greater immunity to tim-
ing jitter, resulting in better signal-to-noise ratio
(SNR) and thus improved BER. In addition,
advanced timing algorithms are used to enable oper-
ation over a wider range of cabling plants.
10Base-T, 100Base-TX, and 1000Base-T
gigabit Ethernet transceiver:
— 0.13 µm process
— 128-pin TQFP and 84-pin MLCC:
❏
RGMII, GMII, MII, RTBI, and TBI interfaces to
MAC or switch
— 68-pin MLCC:
❏
RGMII and RTBI interfaces to MAC or switch
Low power consumption:
— Typical power less than 750 mW in 1000Base-T
mode
— Advanced power management
— ACPI compliant wake-on-LAN support
Oversampling architecture to improve signal integ-
rity and SNR
Optimized, extended performance echo and NEXT
filters
All-digital baseline wander correction
Digital PGA control
On-chip diagnostic support
Automatic speed negotiation
Automatic speed downshift
Single supply 3.3 V or 2.5 V operation:
— On-chip regulator controllers
— 3.3 V or 2.5 V digital I/O
— 3.3 V tolerant I/O pins (MDC, MDIO, COMA,
RESET_N, and JTAG pins)
— 1.0 V or 1.1 V core power supplies
— 1.8 V or 2.5 V for transformer center tap
JTAG
ET1011C is a pin-compatible replacement for the
ET1011 device
Commercial- and industrial-temperature versions
available
■
■
■
■
■
■
■
■
■
■
■
■
TruePHY
ET1011C
Gigabit Ethernet Transceiver
Data Sheet
June 2007
Table of Contents
Contents
Page
Contents
Page
Features ......................................................................1
Introduction..................................................................1
Functional Description .................................................5
Oversampling Architecture .......................................5
Automatic Speed Downshift .....................................5
Transmit Functions...................................................6
Receive Functions....................................................6
Autonegotiation ........................................................7
Carrier Sense (128-Pin TQFP and
84-Pin MLCC Only)...............................................7
Link Monitor..............................................................8
Loopback Mode........................................................9
Digital Loopback.......................................................9
Analog Loopback....................................................10
LEDs.......................................................................11
Regulator Control ...................................................11
Resetting the ET1011C ..........................................11
Low-Power Modes..................................................11
Pin Information ..........................................................12
Pin Diagram, 128-Pin TQFP ..................................12
Pin Diagram, 84-Pin MLCC ....................................13
Pin Diagram, 68-Pin MLCC ...................................14
Pin Descriptions, 128-Pin TQFP, 84-Pin MLCC,
and 68-Pin MLCC ...............................................15
MAC Interface ........................................................22
Management Interface ...........................................27
Configuration Interface ...........................................29
LEDs Interface........................................................31
Media-Dependent Interface:
Transformer Interface .........................................32
Clocking and Reset ................................................33
JTAG ......................................................................34
Regulator Control ...................................................34
Power, Ground, and No Connect ...........................35
Cable Diagnostics......................................................36
Register Description ..................................................37
Register Address Map............................................37
Register Functions/Settings ...................................38
Electrical Specifications.............................................62
Absolute Maximum Ratings....................................62
Recommended Operating Conditions ....................62
Device Electrical Characteristics ............................63
Timing Specification ..................................................67
GMII 1000Base-T Transmit Timing
(128-Pin TQFP and 84-Pin MLCC Only) ............67
GMII 1000Base-T Receive Timing
(128-Pin TQFP and 84-Pin MLCC Only) ............68
RGMII 1000Base-T Transmit Timing......................69
RGMII 1000Base-T Receive Timing.......................71
MII 100Base-TX Transmit Timing...........................73
MII 100Base-TX Receive Timing ...........................74
MII 10Base-T Transmit Timing ...............................75
2
MII 10Base-T Receive Timing ................................76
Serial Management Interface Timing .....................77
Reset Timing ..........................................................78
Clock Timing...........................................................79
JTAG Timing ..........................................................80
Package Diagram, 128-Pin TQFP ............................81
Package Diagram, 84-Pin MLCC .............................82
Package Diagram, 68-Pin MLCC .............................83
Ordering Information .................................................84
Related Documentation..........................................85
Table
Page
Table 1. ET1011C Device Signals
by Interface, 128-Pin TQFP, 84-Pin
and 68-Pin MLCC.................................... 15
Table 2. Multiplexed Signals on the ET1011C .......... 20
Table 3. GMII Signal Description (1000Base-T
Mode) (128-pin TQFP and
84-pin MLCC only) .................................. 22
Table 4. RGMII Signal Description
(1000Base-T Mode) ................................ 23
Table 5. MII Interface (100Base-TX and
10Base-T) (128-Pin TQFP and
84-Pin MLCC Only) ................................. 24
Table 6. Ten-Bit Interface (1000Base-T)
(128-Pin TQFP and 84-Pin MLCC Only) . 25
Table 7. RTBI Signal Description
(1000Base-T Mode) ............................... 26
Table 8. Management Frame Structure .................... 27
Table 9. Management Interface ................................ 28
Table 10. Configuration Signals................................ 29
Table 11. LED .......................................................... 31
Table 12. Transformer Interface Signals................... 32
Table 13. Clocking and Reset................................... 33
Table 14. JTAG Test Interface .................................. 34
Table 15. Regulator Control Interface....................... 34
Table 16. Supply Voltage Combinations ................... 35
Table 17. Power, Ground, and No Connect .............. 35
Table 18. Cable Diagnostic Functions ...................... 36
Table 19. Register Address Map .............................. 37
Table 20. Register Type Definition............................ 37
Table 21. Control Register—Address 0 .................... 38
Table 22. Status Register—Address 1 ...................... 39
Table 23. PHY Identifier Register 1—Address 2........40
Table 24. PHY Identifier Register 2—Address 3........40
Table 25. Autonegotiation Advertisement Register—
Address 4 .................................................41
Table 26. Autonegotiation Link Partner Ability
Register—Address 5 ............................... 42
LSI Corporation
Data Sheet
June 2007
TruePHY
ET1011C
Gigabit Ethernet Transceiver
Table of Contents
(continued)
Table
Page
Table
Page
Table 27. Autonegotiation Expansion Register
—Address 6 ............................................. 43
Table 28. Autonegotiation Next Page Transmit
Register—Address 7................................ 43
Table 29. Link Partner Next Page Register —
Address 8................................................. 44
Table 30. 1000 Base-T Control Register—
Address 9................................................. 45
Table 31. 1000Base-T Status Register—
Address 10............................................... 46
Table 32. Reserved Registers—Addresses 11—14 .. 47
Table 33. Extended Status Register—Address 15 .... 47
Table 34. Reserved Registers—Addresses 16—17.. 47
Table 35. PHY Control Register 2—Address 18 ....... 48
Table 36. MDI/MDI-X Configuration .......................... 49
Table 37. MDI/MDI-X Pin Mapping............................ 49
Table 38. Loopback Control Register—Address 19 .. 50
Table 39. Loopback Bit (0.14) and Cable Diagnostic
Mode Bit (23.13) Settings for
Loopback Mode ....................................... 50
Table 40. RX Error Counter Register—Address 20... 51
Table 41. Management Interface (MI) Control
Register—Address 21.............................. 51
Table 42. PHY Configuration Register—Address 22.52
Table 43. PHY Control Register—Address 23 .......... 53
Table 44. Interrupt Mask Register—Address 24 ....... 54
Table 45. Interrupt Status Register—Address 25 ...... 55
Table 46. PHY Status Register—Address 26 ............ 56
Table 47. LED Control Register 1—Address 27 ........57
Table 48. LED Control Register 2—Address 28 ........58
Table 49. LED Control Register 3—Address 29 ........58
Table 50. Diagnostics Control Register
(TDR Mode)—Address 30 ....................... 59
Table 51. Diagnostics Status Register
(TDR Mode)—Address 31 ....................... 60
Table 52. Diagnostics Control Register
(Link Analysis Mode)—Address 30.......... 61
Table 53. MDI/MDI-X Configuration for 1000Base-T
with C and D Swapped/Not Swapped...... 61
Table 54. Absolute Maximum Ratings ....................... 62
Table 55. ET1011C Recommended
Operating Conditions ............................... 62
Table 56. Device Characteristics—3.3 V
Digital I/O Supply (DVDDIO) ....................63
Table 57. Device Characteristics—2.5 V
Digital I/O Supply (DVDDIO) ....................63
Table 58. ET1011C Current Consumption
GMII 1000Base-T.....................................64
Table 59. ET1011C Current Consumption
GMII 100Base-TX ....................................64
Table 60. ET1011C Current Consumption
GMII 10Base-T.........................................64
Table 61. ET1011C Current Consumption
GMII 10Base-T Idle..................................65
Table 62. ET1011C Current Consumption
RGMII 1000Base-T ..................................65
Table 63. ET1011C Current Consumption
RGMII 100Base-TX..................................65
Table 64. ET1011C Current Consumption
RGMII 10Base-T ......................................66
Table 65. ET1011C Current Consumption
RGMII 10Base-T Idle ...............................66
Table 66. GMII 1000Base-T Transmit Timing............67
Table 67. GMII 1000Base-T Receive Timing.............68
Table 68. RGMII 1000Base-T Transmit Timing .........69
Table 69. RGMII 1000Base-T Transmit Timing .........70
Table 70. RGMII 1000Base-T Receive Timing ..........71
Table 71. RGMII 1000Base-T Receive Timing ..........72
Table 72. MII 100Base-TX Transmit Timing ..............73
Table 73. MII 100Base-TX Receive Timing ...............74
Table 74. MII 10Base-T Transmit Timing...................75
Table 75. MII 10Base-T Receive Timing ...................76
Table 76. Serial Management Interface Timing .........77
Table 77. Reset Timing..............................................78
Table 78. Clock Timing ..............................................79
Table 79. JTAG Timing ..............................................80
Table 80. Ordering Information..................................84
Table 81. Related Documentation .............................85
LSI Corporation
3
TruePHY
ET1011C
Gigabit Ethernet Transceiver
Data Sheet
June 2007
Table of Contents
(continued)
Figure
Contents
Page
Figure
Contents
Page
Figure 1. ET1011C Block Diagram ..............................5
Figure 2. Loopback Functionality.................................9
Figure 3. Digital Loopback...........................................9
Figure 4. Replica and Line Driver Analog Loopback .10
Figure 5. External Cable Loopback ...........................10
Figure 6. Pin Diagram for ET1011C in
128-Pin TQFP Package (Top View) .......12
Figure 7. Pin Diagram for ET1011C in
84-Pin MLCC Package (Top View) .........13
Figure 8. Pin Diagram for ET1011C in
68-Pin MLCC Package (Top View) .........14
Figure 9. ET1011C Gigabit Ethernet Card
Block Diagram ........................................21
Figure 10. GMII MAC-PHY Signals ...........................22
Figure 11. RGMII MAC-PHY Signals .........................23
Figure 12. MII Signals................................................24
Figure 13. Ten-Bit Interface .......................................25
Figure 14. Reduced Ten-Bit Interface........................26
Figure 15. GMII 1000Base-T Transmit Timing ..........67
Figure 16. GMII 1000Base-T Receive Timing ...........68
Figure 17. RGMII 1000Base-T Transmit Timing—
Trace Delay ............................................69
Figure 18. RGMII 1000Base-T Transmit Timing—
Internal Delay .........................................70
Figure 19. RGMII 1000Base-T Receive Timing—
Trace Delay ............................................71
Figure 20. RGMII 1000Base-T Receive Timing—
Internal Delay .........................................72
Figure 21. MII 100Base-TX Transmit Timing .............73
Figure 22. MII 100Base-TX Receive Timing..............74
Figure 23. MII 10Base-T Transmit Timing .................75
Figure 24. MII 10Base-T Receive Timing ..................76
Figure 25. Serial Management Interface Timing........77
Figure 26. Reset Timing ............................................78
Figure 27. Clock Timing.............................................79
Figure 28. JTAG Timing.............................................80
4
LSI Corporation
Data Sheet
June 2007
TruePHY
ET1011C
Gigabit Ethernet Transceiver
Functional Description
The LSI ET1011C is a Gigabit Ethernet transceiver that simultaneously transmits and receives on each of the four
UTP pairs of category 5 cable (signal dimensions or channels A, B, C, and D) at 125 Msymbols/s using five-level
pulse-amplitude modulation (PAM). Figure 1 is a block diagram of its basic configuration.
GTX_CLK
TX_CLK
TXD[7:0]
TX_ER
TX_EN
RX_CLK
RXD[7:0]
RX_ER
RX_DV
COL
CRS
PMA D
PMA C
PMA B
PMA A
RGMII
GMII
MII
RTBI
TBI
BLW
Correction
Gain
Control
Bias
PCS
NEXT
Cancellers
Echo
Canceller
Transmit
Shaping
DAC
Hybrid
TRD[0-3]±
Σ
FFE
ADC
PGA
RSET
Trellis
Decoder
Timing
Control
Auto-
Negotiation
Clock
Generator
LEDS
Config
PHYAD[4:0]
MDC
MDIO
MDINT_N
LEDS/
Config
JTAG/
Test
10BASE-T
Management
Interface
Clock
MI Registers
Reset
TCK
TRST_N
TMS
TDI
TDO
SYS_CLK
XTAL_1
XTAL_2
RESET_N
Figure 1. ET1011C Block Diagram
Oversampling Architecture
The ET1011C architecture uses oversampling tech-
niques to sample at two times the symbol rate. A frac-
tionally spaced feed forward equalizer (FFE) adapts to
remove intersymbol interference (ISI) and to shape the
spectrum of the received signal to maximize the (SNR)
at the trellis decoder input. The FFE equalizes the
channel to a fixed target response. Oversampling
enables the use of a fractionally spaced equalizer
(FSE) structure for the FFE, resulting in symbol rate
clocking for both the FFE and the rest of the receiver.
This provides robust operation and substantial power
savings.
Automatic Speed Downshift
Automatic speed downshift is an enhanced feature of
autonegotiation that allows the ET1011C to:
■
Fallback in speed, based on cabling conditions or
link partner abilities.
Operate over CAT-3 cabling (in 10Base-T mode).
Operate over two-pair CAT-5 cabling (in 100Base-TX
mode).
■
■
For speed fallback, the ET1011C first tries to autonego-
tiate by advertising 1000Base-T capability. After a num-
ber of failed attempts to bring up the link, the ET1011C
falls back to advertising 100Base-TX and restarts the
autonegotiation process. This process continues
through all speeds down to 10Base-T. At this point,
there are no lower speeds to try and so the host
enables all technologies and starts again.
PHY configuration register, address 22, bits 11 and 10
enable automatic speed downshift and specifies if fall-
back to 10Base-T is allowed. PHY control register,
address 23, bits 11 and 12 specify the number of failed
attempts before downshift (programmable to 1, 2, 3, or
4 attempts).
LSI Corporation
5
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
