KP18GB256-SP
Super Permanent Memory
Features Summary
•
•
•
•
•
•
One time electrically field
programmable non-volatile CMOS
embedded memory
Delivered as hard IP core
Manufacturable in UMC 0.18 µm standard
logic CMOS process technology (L180)
Data bus interface
- 8-bits in parallel read
- 1-bit in serial write
Read operating voltage
- V
DD
= 1.8V
±
0.2V
- V
DDHI
= 3.3V
±
0.3V
Programming voltage with charge pump:
-
V
DD
= 1.8V
±
0.2V
-
V
DDHI
= 3.3V
±
0.3V
•
•
•
•
•
•
•
Low power consumption
Density 256K-bits:
- Active read: 5mA max @ 5MHz
- Standby: 1µA typ.
Fast read access time:
- t
ACC
≤
75ns
High density
- 0.9 mm square (w/ charge pump)
Fast interactive programming algorithm
Programming time
- 50µs per bit (typ).
Suitable for on-board programming
High reliability
- Data retention:
≥100
years
Summary Description
The KP18GB256-SP is an embedded non-volatile
one-time programmable (OTP) Super Permanent
Memory (XPM) IP core. The memory is arranged
in a 32K x 8 read configuration and a 256K x 1
write configuration:
1. 8-bit parallel data read interface.
2. 1-bit serial data write interface.
The
KP18GB256-SP
is implemented using Kilopass
Technology’s advanced XPM technology in 0.18 um
standard CMOS logic process.
The operation of the XPM memory block is defined
below:
The Chip Enable signal controls the operation of
the memory. A set of input signals controls the read
and program operation of the memory. On
power-up, the memory defaults to read mode.
KP18GB256-SP
rev. 0.992 –
Preliminary
1
July 13, 2003
KP18GB256-SP
Block Diagram
V
PP
(optional)
Address
Bus
X-Decoder
Cell Array
V
DDHI
V
DD
V
SS
Y-Decoder
Y-Gating
8
READEN
Control Logic
R/W CKT
I/O Buffer
D[0:7]
PGMEN
CEB
CLE
DLE
WEB
RSTB
CPUMPEN
DIN
Configuration: Serial Write / Parallel Read Data Bus Interface
KP18GB256-SP
rev. 0.992 –
Preliminary
2
July 13, 2003
KP18GB256-SP
Pin Configurations
Pin Names
IO Signals
A [17:0]
A [17:3]
CEB
CLE
DLE
PGMEN
READEN
RSTB
WEB
CPUMPEN
D [0:7]
DIN
Power Supplies
V
DDHI
V
DD
V
SS
Direction
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
Input Power
Input Power
Input Power
Functions
Bit address input for programming
Byte address input for read
Chip Enable, Active Low
Command Latch Enable (for test)
Data Latch Enable
Program Enable
Read Enable
Module Reset. Active Low
Write Enable. Active Low
Selects Charge Pump Programming Mode. Active High
Parallel interface. Data output in read mode
Serial write interface
IO Power Supply (3.3V)
Core Power Supply (1.8V)
Ground (0V)
Pin Description
A [17:0]
These address pins are divided into several
groups (row address, column address, sector
address, etc) according to the bit map.
CEB
CEB active low is the chip enable to power control
and should be used for block selection.
CLE
CLE enables test mode command entry. User
can write to the corresponding test mode
command registers using test mode command
sequence.
DLE
DLE enables data input buffers and allows
program data patterns to be written into these
buffers. This signal is combined with others
during program mode.
PGMEN
PGMEN active high will enable the high voltage
circuit on chip for programming. Please refer to
program command sequence for correct
waveforms.
CPUMPEN
CPUMPEN selects the charge pump programming
mode. Must remain low for programming XPM
using external V
PP
programming voltage. Active
high for programming using internal charge pump
programming mode.
READEN
READEN must be high during read mode and
low during program mode.
During program mode, READEN must be low
to power down sense the amplifiers for circuit
protection.
KP18GB256-SP
rev. 0.992 –
Preliminary
3
July 13, 2003
KP18GB256-SP
RSTB
RSTB active low will reset all test command
registers and data input buffers. This pin must be
clocked before any test mode entry and clocked
to clear the old setting and old data in the
program mode.
WEB
device to perform a command sequence and
program data sequence in test mode and
programming mode respectively.
D [7:0]
The parallel data bus interface.
DIN
The serial write data interface.
WEB is a negative pulse which allows the
Functional Descriptions
Programming Mode
When the KP18GB256-SP is instantiated, the
device has all bits in the “1”s, or HIGH state.
“0”s are loaded into the device through
programming.
The programming mode is entered when PGMEN
is asserted high and WEB is at V
IL.
The data to be
programmed is applied serially in serial write
configurations. The fast interactive programming
algorithm reduces programming time. After the
data is latched in the register, PGMEN is raised to
high in order to program each memory cell. After
each programming pulse is applied
to a given
address, the data at that address should be
verified. If the data is not verified, additional
pulses should be given until it is verified or until
the maximum number of pulses is reached. After
the final address is completed, the entire device
is read to verify all stored data.
Program Inhibit Mode
A high level input on the WEB will inhibit the
device from being programmed.
Read Mode
The read mode is entered when the READEN
and WEB are at V
IH.
Assuming that addresses
are stable, address access time (t
ACC)
is equal to
the delay from READEN to outputs (t
READEN
).
Standby Mode
The KP18GB256-SP has a standby mode, which
reduces the maximum V
DD
current to 1 uA.
KP18GB256-SP
rev. 0.992 –
Preliminary
4
July 13, 2003
KP18GB256-SP
D.C. Characteristics
Symbol
Read Operation
V
OH
V
OL
V
IH
V
IL
I
LI
I
LO
I
DD
I
DDHI
I
SB
V
OH
V
OL
V
IH
V
IL
I
LI
I
LO
I
DD
I
DDHI
Capacitance
C
IN
C
OUT
Input Capacitance
Output Capacitance
-
-
-
-
-
-
-
-
-
-
1
2
pF
pF
Output High Level
Output Low Level
Input High Level
Input Low Level
Input Leakage
Current
Output Leakage
Current
V
DD
Active Current
V
DDHI
Active Current
Standby Current
Output High Level
Output Low Level
Input High Level
Input Low Level
Input Leakage
Current
Output Leakage
Current
V
DD
Active Current
V
DDHI
Active Current
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
-
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
IN
=0 to 2.0V
V
OUT
=0 to 2.0V
V
DD
– 0.2
0
V
DD
– 0.2
-
0.2
Parameter
Test Conditions
V
DD
V
DDIO
Conditions
Min.
Typ.
Max.
Unit
-
-
-
-
-
-
-
-
1.0
-
-
-
-
-
-
-
-
V
DD
0.2
V
DD
+ 0.2
0.2
3
5
1.67
3.33
10
V
DD
0.2
V
DD
+ 0.2
0.2
5.0
5
1.67
3.33
V
V
V
V
µA
µA
mA
mA
µA
V
V
V
V
µA
µA
mA
mA
-
-
-
-
-
V
DD
– 0.2
0
V
DD
– 0.2
-
0.2
-
3.3V
CEB
=V
IL
, f=5MHz
CEB
=V
IL
, f=5MHz
CEB
=V
IH
-
-
-
-
V
IN
=V
IL
, V
IH
V
OUT
=0 to 2.0V
Programming Operation
-
-
-
-
-
3.3V
CEB
=V
IL
CEB
=V
IL
KP18GB256-SP
rev. 0.992 –
Preliminary
5
July 13, 2003
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