INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT243
Quad bus transceiver; 3-state
Product specification
File under Integrated Circuits, IC06
December 1990
Philips Semiconductors
Product specification
Quad bus transceiver; 3-state
FEATURES
•
Non-inverting 3-state outputs
•
2-way asynchronous data bus communication
•
Output capability: bus driver
•
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT243 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
74HC/HCT243
The 74HC/HCT243 are quad bus transceivers featuring
non-inverting 3-state bus compatible outputs in both send
and receive directions.
They are designed for 4-line asynchronous 2-way data
communications between data buses.
The output enable inputs (OE
A
and OE
B
) can be used to
isolate the buses.
The “243” is similar to the “242” but has non-inverting (true)
outputs.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns
TYPICAL
SYMBOL
t
PHL/
t
PLH
PARAMETER
propagation delay
A
n
to B
n
;
B
n
to A
n
input capacitance
input/output capacitance
power dissipation capacitance per transceiver notes 1 and 2
CONDITIONS
HC
C
L
= 15 pF; V
CC
= 5 V
6
HCT
11
ns
UNIT
C
I
C
I/O
C
PD
Notes
3.5
10
26
3.5
10
34
pF
pF
pF
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
−
1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2
Philips Semiconductors
Product specification
Quad bus transceiver; 3-state
PIN DESCRIPTION
PIN NO.
1
2, 12
3, 4, 5, 6
7
11, 10, 9, 8
13
14
SYMBOL
OE
A
n.c.
A
0
to A
3
GND
B
0
to B
3
OE
B
V
CC
NAME AND FUNCTION
output enable input (active LOW)
not corrected
data inputs/outputs
ground (0 V)
data inputs/outputs
output enable input
positive supply voltage
74HC/HCT243
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
Quad bus transceiver; 3-state
FUNCTION TABLE
INPUTS
OE
A
L
H
L
H
Notes
OE
B
L
L
H
H
A
n
inputs
Z
Z
A=B
74HC/HCT243
INPUTS/OUTPUTS
B
n
B=A
Z
Z
inputs
1. H = HIGH voltage level
L = LOW voltage level
Z = high impedance OFF-state
Fig.4 Functional diagram.
December 1990
4
Philips Semiconductors
Product specification
Quad bus transceiver; 3-state
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: bus driver
I
CC
category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
T
amb
(°C)
74HC
SYMBOL PARAMETER
min.
74HC/HCT243
TEST CONDITIONS
UNIT V
WAVEFORMS
CC
(V)
ns
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Fig.5
+25
−40
to
+85
−40
to
+125
min.
max.
135
27
23
225
45
38
250
50
43
90
18
15
typ. max. min. max.
t
PHL
/ t
PLH
propagation delay
A
n
to B
n
;
B
n
to A
n
3-state output enable time
OE
A
to A
n
or B
n;
OE
B
to A
n
or B
n
3-state output disable time
OE
A
to A
n
or B
n;
OE
B
to A
n
or B
n
output transition time
22
8
6
50
18
14
61
22
18
14
5
4
90
18
15
150
30
26
165
33
28
60
12
10
115
23
20
190
38
33
205
41
35
75
15
13
t
PZH
/ t
PZL
ns
Figs 6 and 7
t
PHZ
/ t
PLZ
ns
Figs 6 and 7
t
THL
/ t
TLH
ns
Fig.5
December 1990
5
聊聊、笑笑、闹闹
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
