MAX 7000A
®
Includes
MAX 7000AE
Programmable Logic
Device Family
Data Sheet
May 2000, ver. 3.01
Features...
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High-performance 3.3-V EEPROM-based programmable logic
devices (PLDs) built on second-generation Multiple Array MatriX
(MAX
®
) architecture (see
Table 1)
3.3-V in-system programmability (ISP) through the built-in
IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with
advanced pin-locking capability
Built-in boundary-scan test (BST) circuitry compliant with
IEEE Std. 1149.1
Supports JEDEC Jam Standard Test and Programming Language
(STAPL) JESD-71
Enhanced ISP features
–
Enhanced ISP algorithm for faster programming (excluding
EPM7128A and EPM7256A devices)
–
ISP_Done bit to ensure complete programming (excluding
EPM7128A and EPM7256A devices)
–
Pull-up resistor on I/O pins during in-system programming
Pin-compatible with the popular 5.0-V MAX 7000S devices
High-density PLDs ranging from 600 to 10,000 usable gates
4.5-ns pin-to-pin logic delays with counter frequencies of up to
227.3 MHz
f
For information on in-system programmable 5.0-V MAX 7000 or 2.5-V
MAX 7000B devices, see the
MAX 7000 Programmable Logic Device Family
Data Sheet
or the
MAX 7000B Programmable Logic Device Family Data Sheet.
Table 1. MAX 7000A Device Features
Feature
Usable gates
Macrocells
Logic array blocks
Maximum user I/O
pins
t
PD
(ns)
t
SU
(ns)
t
FSU
(ns)
t
CO1
(ns)
f
CNT
(MHz)
Altera Corporation
A-DS-M7000A-03.01
EPM7032AE
600
32
2
36
4.5
2.9
2.5
3.0
227.3
EPM7064AE
1,250
64
4
68
4.5
2.8
2.5
3.1
222.2
EPM7128AE
EPM7128A
2,500
128
8
100
5.0
3.3
2.5
3.4
192.3
EPM7256AE
EPM7256A
5,000
256
16
164
5.5
3.9
2.5
3.5
172.4
EPM7512AE
10,000
512
32
212
7.5
5.6
3.0
4.7
116.3
1
MAX 7000A Programmable Logic Device Family Data Sheet
...and More
Features
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MultiVolt
TM
I/O interface enables device core to run at 3.3 V, while
I/O pins are compatible with 5.0-V, 3.3-V, and 2.5-V logic levels
Pin counts ranging from 44 to 256 in a variety of thin quad flat pack
(TQFP), plastic quad flat pack (PQFP), ball-grid array (BGA), space-
saving FineLine BGA
TM
, and plastic J-lead chip carrier (PLCC)
packages
Supports hot-socketing in MAX 7000AE devices
Programmable interconnect array (PIA) continuous routing structure
for fast, predictable performance
Peripheral component interconnect (PCI)-compatible
Bus-friendly architecture, including programmable slew-rate control
Open-drain output option
Programmable macrocell registers with individual clear, preset,
clock, and clock enable controls
Programmable power-up states for macrocell registers in
MAX 7000AE devices
Programmable power-saving mode for 50% or greater power
reduction in each macrocell
Configurable expander product-term distribution, allowing up to
32 product terms per macrocell
Programmable security bit for protection of proprietary designs
6 to 10 pin- or logic-driven output enable signals
Two global clock signals with optional inversion
Enhanced interconnect resources for improved routability
Fast input setup times provided by a dedicated path from I/O pin to
macrocell registers
Programmable output slew-rate control
Programmable ground pins
Software design support and automatic place-and-route provided by
Altera’s development systems for Windows-based PCs and Sun
SPARCstation, HP 9000 Series 700/800, and IBM RISC System/6000
workstations
Additional design entry and simulation support provided by EDIF
2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),
Verilog HDL, VHDL, and other interfaces to popular EDA tools from
manufacturers such as Cadence, Exemplar Logic, Mentor Graphics,
OrCAD, Synopsys, Synplicity, and VeriBest
Programming support with Altera’s Master Programming Unit
(MPU), BitBlaster
TM
serial download cable, ByteBlaster
TM
parallel
port download cable, ByteBlasterMV
TM
parallel port download cable,
and MasterBlaster
TM
serial/universal serial bus (USB)
communications cable, as well as programming hardware from
third-party manufacturers and any Jam
TM
STAPL File (.jam), Jam
Byte-Code File (.jbc), or Serial Vector Format File- (.svf) capable
in-circuit tester (the ByteBlaster cable is obsolete and is replaced by
the ByteBlasterMV cable)
2
Altera Corporation
MAX 7000A Programmable Logic Device Family Data Sheet
General
Description
MAX 7000A (including MAX 7000AE) devices are high-density, high-
performance devices based on Altera’s second-generation MAX
architecture. Fabricated with advanced CMOS technology, the EEPROM-
based MAX 7000A devices operate with a 3.3-V supply voltage and
provide 600 to 10,000 usable gates, ISP, pin-to-pin delays as fast as 4.5 ns,
and counter speeds of up to 227.3 MHz. MAX 7000A devices in the -4, -5,
-6, -7 and some -10 speed grades are compatible with the timing
requirements for 33 MHz operation of the PCI Special Interest Group (PCI
SIG)
PCI Local Bus Specification, Revision 2.2.
See
Table 2.
Table 2. MAX 7000A Speed Grades
Device
-4
EPM7032AE
EPM7064AE
EPM7128A
EPM7128AE
EPM7256A
EPM7256AE
EPM7512AE
Speed Grade
-5
-6
-7
v
v
v
v
v
v
v
v
v
v
-10
v
v
v
v
v
v
v
v
v
v
-12
v
v
The MAX 7000A architecture supports 100% transistor-to-transistor logic
(TTL) emulation and high-density integration of SSI, MSI, and LSI logic
functions. It easily integrates multiple devices including PALs, GALs, and
22V10s devices. MAX 7000A devices are available in a wide range of
packages, including PLCC, BGA, FineLine BGA, Ultra FineLine BGA,
PQFP, and TQFP packages. See
Table 3
and
Table 4.
Table 3. MAX 7000A Maximum User I/O Pins
Device
44-Pin
PLCC
44-Pin
TQFP
49-Pin
Ultra
FineLine
BGA
40
(4)
Notes (1), (2)
84-Pin
PLCC
100-Pin 100-Pin
TQFP FineLine
BGA
(3)
EPM7032AE
EPM7064AE
EPM7128A
EPM7128AE
EPM7256A
EPM7256AE
EPM7512AE
Altera Corporation
36
36
36
36
68
68
68
84
84
84
84
84
68
84
84
3
MAX 7000A Programmable Logic Device Family Data Sheet
Table 4. MAX 7000A Maximum User I/O Pins
Device
144-Pin
TQFP
169-Pin
Ultra
FineLine
BGA
Notes (1), (2)
256-Pin
BGA
256-Pin
FineLine
BGA
(3)
68
208-Pin
PQFP
EPM7032AE
EPM7064AE
EPM7128A
EPM7128AE
EPM7256A
EPM7256AE
EPM7512AE
Notes:
(1)
(2)
(3)
100
100
100
120
120
120
100
(4)
164
164
176
176
212
212
100
100
164
164
212
212
(4)
Contact Altera for up-to-date information on available device package options.
When the IEEE Std. 1149.1 (JTAG) interface is used for in-system programming or
boundary-scan testing, four I/O pins become JTAG pins.
All FineLine BGA packages are footprint-compatible via the SameFrame
TM
feature.
Therefore, designers can design a board to support a variety of devices, providing
a flexible migration path across densities and pin counts. Device migration is fully
supported by Altera development tools. See
“SameFrame Pin-Outs” on page 14
for
more details.
This information is preliminary.
MAX 7000A devices use CMOS EEPROM cells to implement logic
functions. The user-configurable MAX 7000A architecture accommodates
a variety of independent combinatorial and sequential logic functions.
The devices can be reprogrammed for quick and efficient iterations
during design development and debug cycles, and can be programmed
and erased up to 100 times.
MAX 7000A devices contain from 32 to 512 macrocells that are combined
into groups of 16 macrocells, called logic array blocks (LABs). Each
macrocell has a programmable-AND/fixed-OR array and a configurable
register with independently programmable clock, clock enable, clear, and
preset functions. To build complex logic functions, each macrocell can be
supplemented with both shareable expander product terms and high-
speed parallel expander product terms, providing up to 32 product terms
per macrocell.
4
Altera Corporation
MAX 7000A Programmable Logic Device Family Data Sheet
MAX 7000A devices provide programmable speed/power optimization.
Speed-critical portions of a design can run at high speed/full power,
while the remaining portions run at reduced speed/low power. This
speed/power optimization feature enables the designer to configure one
or more macrocells to operate at 50% or lower power while adding only a
nominal timing delay. MAX 7000A devices also provide an option that
reduces the slew rate of the output buffers, minimizing noise transients
when non-speed-critical signals are switching. The output drivers of all
MAX 7000A devices can be set for 2.5 V or 3.3 V, and all input pins are
2.5-V, 3.3-V, and 5.0-V tolerant, allowing MAX 7000A devices to be used
in mixed-voltage systems.
MAX 7000A devices are supported by Altera development systems,
which are integrated packages that offer schematic, text—including
VHDL, Verilog HDL, and the Altera Hardware Description Language
(AHDL)—and waveform design entry, compilation and logic synthesis,
simulation and timing analysis, and device programming. The software
provides EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL, and other
interfaces for additional design entry and simulation support from other
industry-standard PC- and UNIX-workstation-based EDA tools. The
software runs on Windows-based PCs, as well as Sun SPARCstation, HP
9000 Series 700/800, and IBM RISC System/6000 workstations.
f
Functional
Description
For more information on development tools, see the
MAX+PLUS II
Programmable Logic Development System & Software Data Sheet
and the
Quartus Programmable Logic Development System & Software Data Sheet.
The MAX 7000A architecture includes the following elements:
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Logic array blocks (LABs)
Macrocells
Expander product terms (shareable and parallel)
Programmable interconnect array
I/O control blocks
The MAX 7000A architecture includes four dedicated inputs that can be
used as general-purpose inputs or as high-speed, global control signals
(clock, clear, and two output enable signals) for each macrocell and I/O
pin.
Figure 1
shows the architecture of MAX 7000A devices.
Altera Corporation
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