19-3546; Rev 2; 10/08
KIT
ATION
EVALU
BLE
AVAILA
12-Bit, 500Msps Interpolating and Modulating
Dual DAC with CMOS Inputs
General Description
The MAX5893 programmable interpolating, modulating,
500Msps, dual digital-to-analog converter (DAC) offers
superior dynamic performance and is optimized for high-
performance wideband, single-carrier transmit applica-
tions. The device integrates a selectable 2x/4x/8x
interpolating filter, a digital quadrature modulator, and
dual 12-bit high-speed DACs on a single integrated cir-
cuit. At 30MHz output frequency and 500Msps update
rate, the in-band SFDR is 84dBc while consuming 1.1W.
The device also delivers 72dB ACLR for single-carrier
WCDMA at a 61.44MHz output frequency.
The selectable interpolating filters allow lower input data
rates while taking advantage of the high DAC update
rates. These linear-phase interpolation filters ease
reconstruction filter requirements and enhance the
passband dynamic performance. Individual offset and
gain programmability allow the user to calibrate out local
oscillator (LO) feedthrough and sideband suppression
errors generated by analog quadrature modulators.
The MAX5893 features a f
IM
/4 digital image-reject mod-
ulator. This modulator generates a quadrature-modulat-
ed IF signal that can be presented to an analog I/Q
modulator to complete the upconversion process. A
second digital modulation mode allows the signal to be
frequency-translated with image pairs at f
IM
/2 or f
IM
/4.
The MAX5893 features a standard 1.8V CMOS, 3.3V tol-
erant data input bus for easy interface. A 3.3V SPI™ port
is provided for mode configuration. The programmable
modes include the selection of 2x/4x/8x interpolating fil-
ters, f
IM
/2, f
IM
/4 or no digital quadrature modulation with
image rejection, channel gain and offset adjustment, and
offset binary or two’s complement data interface.
Pin-compatible 14- and 16-bit devices are also available.
Refer to the MAX5894 data sheet for the 14-bit version
and the MAX5895 data sheet for the 16-bit version.
Features
o
72dB ACLR at f
OUT
= 61.44MHz (Single-Carrier
WCDMA)
o
Meets 3G UMTS, cdma2000
®
, GSM Spectral Masks
(f
OUT
= 122MHz)
o
Noise Spectral Density = -151dBFS/Hz at
f
OUT
= 16MHz
o
90dBc SFDR at Low-IF Frequency (10MHz)
o
86dBc SFDR at High-IF Frequency (50MHz)
o
Low Power: 511mW (f
CLK
= 100MHz)
o
User Programmable
Selectable 2x, 4x, or 8x Interpolating Filters
< 0.01dB Passband Ripple
> 99dB Stopband Rejection
Selectable Real or Complex Modulator Operation
Selectable Modulator LO Frequency: OFF, f
IM
/2,
or f
IM
/4
Selectable Output Filter: Lowpass or Highpass
Channel Gain and Offset Adjustment
o
EV Kit Available (Order the MAX5893EVKIT)
MAX5893
Ordering Information
PART
MAX5893EGK-D
MAX5893EGK+D
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
68 QFN-EP*
68 QFN-EP*
D = Dry pack.
*EP
= Exposed pad.
+Denotes
a lead-free/RoHS-compliant package.
Selector Guide
PART
MAX5893
MAX5894
MAX5895
MAX5898
RESOLUTION
(BITS)
12
14
16
16
DAC UPDATE
RATE (Msps)
500
500
500
500
INPUT
LOGIC
CMOS
CMOS
CMOS
LVDS
Applications
Base Stations: 3G UMTS, CDMA, and GSM
Broadband Wireless Transmitters
Broadband Cable Infrastructure
Instrumentation and Automatic Test Equipment (ATE)
Analog Quadrature Modulation Architectures
Simplified Diagram
DATA
PORT A
OUTI
DAC
1x/2x/4x
INTERPOLATING
FILTERS
2x
INTERPOLATING
FILTERS
MODULATOR
DATA SYNCH
AND DEMUX
Pin Configuration appears at end of data sheet.
DATACLK
SPI is a trademark of Motorola, Inc.
cdma2000 is a registered trademark of Telecommunications
Industry Association.
DATA
PORT B
DAC
OUTQ
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
12-Bit, 500Msps Interpolating and Modulating
Dual DAC with CMOS Inputs
MAX5893
ABSOLUTE MAXIMUM RATINGS
DV
DD1.8
, AV
DD1.8
to GND, DACREF ..................-0.3V to +2.16V
AV
DD3.3
, AV
CLK
, DV
DD3.3
to GND, DACREF ........-0.3V to +3.9V
DATACLK, A0–A11, B0–B9,
SELIQ/B11, DATACLK/B10,
CS, RESET,
SCLK,
SDI and SDO to GND, DACREF......-0.3V to (DV
DD3.3
+ 0.3V)
CLKP, CLKN to GND, DACREF..............-0.3V to (AV
CLK
+ 0.3V)
REFIO, FSADJ to GND, DACREF ........-0.3V to (AV
DD3.3
+ 0.3V)
OUTIP, OUTIN, OUTQP,
OUTQN to GND, DACREF..................-1V to (AV
DD3.3
+ 0.3V)
SDO, DATACLK, DATACLK/BIO Continuous Current ..........8mA
Continuous Power Dissipation (T
A
= +70°C)
68-Pin QFN (derate 41.7mW/°C above +70°C)
(Note 1) ...................................................................3333.3mW
Junction Temperature ......................................................+150°C
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Thermal Resistance
θ
JC
(Note 1)....................................0.8°C/W
Note 1:
Thermal resistance based on a multilayer board with 4 x 4 via array in exposed pad area.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(DV
DD1.8
= AV
DD1.8
= 1.8V, AV
CLK
= AV
DD3.3
= DV
DD3.3
= 3.3V, modulator off, 2x interpolation, DATACLK input mode, dual-port
mode, 50Ω double-terminated outputs, external reference at 1.25V, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are
at T
A
= +25°C, unless otherwise noted.) (Note 2)
PARAMETER
STATIC PERFORMANCE
Resolution
Differential Nonlinearity
Integral Nonlinearity
Offset Error
Offset Drift
Full-Scale Gain Error
Gain-Error Drift
Full-Scale Output Current
Output Compliance
Output Resistance
Output Capacitance
DYNAMIC PERFORMANCE
Maximum Clock Frequency
Minimum Clock Frequency
Maximum DAC Update Rate
Minimum DAC Update Rate
Maximum Input Data Rate
f
CLK
f
CLK
f
DAC
f
DAC
f
DATA
f
DATACLK
= 125MHz,
f
OUT
= 16MHz, f
OFFSET
= 10MHz, -12dBFS
Noise Spectral Density
f
DATACLK
= 125MHz,
f
OUT
= 16MHz, f
OFFSET
= 10MHz, 0dBFS
No interpolation
2x interpolation
4x interpolation
4x interpolation
f
DAC
= f
CLK
or f
DAC
= f
CLK
/2
f
DAC
= f
CLK
or f
DAC
= f
CLK
/2
125
-151
-147
-148
-145
dBFS/
Hz
500
1
500
1
MHz
MHz
Msps
Msps
MWps
R
OUT
C
OUT
I
OUTFS
2
-0.5
1
5
GE
FS
-4
DNL
INL
OS
-0.025
12
±0.5
±1
±0.003
±0.03
±0.6
±110
20
+1.1
+4
+0.025
Bits
LSB
LSB
%FS
ppm/°C
%FS
ppm/°C
mA
V
MΩ
pF
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
2
_______________________________________________________________________________________
12-Bit, 500Msps Interpolating and Modulating
Dual DAC with CMOS Inputs
ELECTRICAL CHARACTERISTICS (continued)
(DV
DD1.8
= AV
DD1.8
= 1.8V, AV
CLK
= AV
DD3.3
= DV
DD3.3
= 3.3V, modulator off, 2x interpolation, DATACLK input mode, dual-port
mode, 50Ω double-terminated outputs, external reference at 1.25V, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are
at T
A
= +25°C, unless otherwise noted.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
f
DATACLK
= 125MHz,
interpolation off, 0dBFS
f
OUT
= 10MHz
f
OUT
= 30MHz
f
OUT
= 50MHz
In-Band SFDR
(DC to f
DATA
/2)
SFDR
f
DATACLK
= 125MHz,
2x interpolation, 0dBFS
f
OUT
= 10MHz
f
OUT
= 30MHz
f
OUT
= 50MHz
f
DATACLK
= 125MHz,
4x interpolation, 0dBFS
f
DATACLK
= 125MHz,
f
OUT1
= 9MHz, f
OUT2
=
10MHz, -6.1dBFS
f
OUT
= 10MHz
f
OUT
= 30MHz
f
OUT
= 50MHz
No interpolation
2x interpolation
4x interpolation
77
MIN
TYP
90
83
72
88
83
84
90
84
86
-100
-100
-100
-73
dBc
MAX
UNITS
MAX5893
2x interpolation,
f
IM
/4 complex
f
DATA
= 125MHz, f
OUT1
modulation
= 79MHz, f
OUT2
=
4x interpolation,
80MHz, -6.1dBFS
f
IM
/4 complex
modulation
Two-Tone IMD
TTIMD
f
DATACLK
= 62.5MHz,
f
OUT1
= 9MHz, f
OUT2
=
10MHz, -6.1dBFS
f
DATACLK
= 62.5MHz,
f
OUT1
= 69MHz, f
OUT2
= 70MHz, -6.1dBFS
-75
dBc
8x interpolation
-99
8x interpolation,
f
IM
/4 complex
modulation
-67
8x, highpass
f
DATACLK
= 62.5MHz,
interpolation,
f
OUT1
= 179MHz, f
OUT2
f
IM
/4 complex
= 180MHz, -6.1dBFS
modulation
f
DATACLK
= 125MHz, f
OUT
spaced 1MHz
apart from 32MHz, -12dBFS, 2x
interpolation
f
DATACLK
= 61.44MHz,
f
OUT
= baseband
ACLR for WCDMA
(Note 3)
f
DATACLK
=
122.88MHz, f
OUT
=
61.44MHz
f
DATACLK
=
122.88MHz, f
OUT
=
122.88MHz
4x interpolation
8x interpolation
2x interpolation,
f
IM
/4 complex
modulation
4x interpolation,
f
IM
/4 complex
modulation
-62
Four-Tone IMD
FTIMD
-93
74
73
73
dBc
ACLR
dB
69
_______________________________________________________________________________________
3
12-Bit, 500Msps Interpolating and Modulating
Dual DAC with CMOS Inputs
MAX5893
ELECTRICAL CHARACTERISTICS (continued)
(DV
DD1.8
= AV
DD1.8
= 1.8V, AV
CLK
= AV
DD3.3
= DV
DD3.3
= 3.3V, modulator off, 2x interpolation, DATACLK input mode, dual-port
mode, 50Ω double-terminated outputs, external reference at 1.25V, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are
at T
A
= +25°C, unless otherwise noted.) (Note 2)
PARAMETER
Output Propagation Delay
Output Rise Time
Output Fall Time
Output Settling Time
Output Bandwidth
Passband Width
SYMBOL
t
PD
t
RISE
t
FALL
CONDITIONS
1x interpolation (Note 4)
10% to 90% (Note 5)
10% to 90% (Note 5)
To 0.5% (Note 5)
-1dB bandwidth (Note 6)
Ripple < -0.01dB
0.604 x f
DATA
, 2x interpolation
Stopband Rejection
0.604 x f
DATA
, 4x interpolation
0.604 x f
DATA
, 8x interpolation
1x interpolation
Data Latency
2x interpolation
4x interpolation
8x interpolation
DAC INTERCHANNEL MATCHING
Gain Match
Gain-Match Tempco
Phase Match
Phase-Match Tempco
DC Gain Match
Channel-to-Channel Crosstalk
REFERENCE
Reference Input Range
Reference Output Voltage
Reference Input Resistance
Reference Voltage Drift
CMOS LOGIC INPUT/OUTPUT (A11–A0, SELIQ/B11, DATACLK/B10, B9–B0, DATACLK)
Input High Voltage
Input Low Voltage
Input Current
Input Capacitance
V
IH
V
IL
I
IN
C
IN
±1
3
0.7 x
DV
DD1.8
0.3 x
DV
DD1.8
±20
V
V
µA
pF
V
REFIO
R
REFIO
Internal reference
0.125
1.14
1.20
10
±50
1.250
1.27
V
V
kΩ
ppm/°C
∆Gain
∆Gain/°C
∆Phase
f
OUT
= DC - 80MHz, I
OUTFS
= 20mA
I
OUTFS
= 20mA
f
OUT
= 60MHz, I
OUTFS
= 20mA
I
OUTFS
= 20mA
f
OUT
= 50MHz, f
DAC
= 250MHz, 0dBFS
-0.2
±0.1
±0.02
±0.13
±0.006
±0.04
-90
+0.2
dB
ppm/°C
Deg
Deg/°C
dB
dB
MIN
TYP
2.9
0.75
1
11
240
0.4 x
f
DATA
100
100
100
22
70
146
311
Clock
Cycles
dB
MAX
UNITS
ns
ns
ns
ns
MHz
∆Phase/°C
f
OUT
= 60MHz, I
OUTFS
= 20mA
4
_______________________________________________________________________________________
12-Bit, 500Msps Interpolating and Modulating
Dual DAC with CMOS Inputs
ELECTRICAL CHARACTERISTICS (continued)
(DV
DD1.8
= AV
DD1.8
= 1.8V, AV
CLK
= AV
DD3.3
= DV
DD3.3
= 3.3V, modulator off, 2x interpolation, DATACLK input mode, dual-port
mode, 50Ω double-terminated outputs, external reference at 1.25V, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are
at T
A
= +25°C, unless otherwise noted.) (Note 2)
PARAMETER
Output High Voltage
Output Low Voltage
Output Leakage Current
Rise/Fall Time
CLOCK INPUT (CLKP, CLKN)
Differential Input Voltage Swing
Differential Input Slew Rate
Common-Mode Voltage
Input Resistance
Input Capacitance
Minimum Clock Duty Cycle
Maximum Clock Duty Cycle
CLKP/CLKN, DATACLK TIMING (Figure 4) (Notes 7, 8)
CLK to DATACLK Delay
Data Hold Time, DATACLK
Input/Output (Pin 14)
Data Setup Time, DATACLK
Input/Output (Pin 14)
Data Hold Time, DATACLK/B10
Input/Output (Pin 27)
Data Setup Time, DATACLK/B10
Input/Output (Pin 27)
SCLK Frequency
CS
Setup Time
Input Hold Time
Input Setup Time
Data Valid Duration
t
D
t
DH
t
DS
t
DH
t
DS
DATACLK output mode, C
LOAD
= 10pF
Capturing rising edge
Capturing falling edge
Capturing rising edge
Capturing falling edge
Capturing rising edge
Capturing falling edge
Capturing rising edge
Capturing falling edge
1.0
2.1
0.4
-0.7
1.0
2.3
0.2
-0.4
10
2.5
0
4.5
6.5
16.5
6.2
ns
ns
ns
ns
ns
V
COM
R
CLK
C
CLK
AC-coupled
V
DIFF
Sine-wave input
Square-wave input
> 1.5
> 0.5
> 100
AV
CLK
/2
5
3
45
55
V
P-P
V/µs
V
kΩ
pF
%
%
SYMBOL
V
OH
V
OL
200µA load
200µA load
Three-state
C
LOAD
= 10pF, 20% to 80%
1
1.6
CONDITIONS
MIN
0.8 x
DV
DD3.3
0.2 x
DV
DD3.3
TYP
MAX
UNITS
V
V
µA
ns
MAX5893
SERIAL PORT INTERFACE TIMING (Figure 3) (Note 7)
f
SCLK
t
SS
t
SDH
t
SDS
t
SDV
MHz
ns
ns
ns
ns
_______________________________________________________________________________________
5
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