CAT93HC46
1K-Bit High Speed Microwire Serial EEPROM
FEATURES
s
High speed operation:
s
Software write protection
H
GEN
FR
ALO
EE
LE
A
D
F
R
E
E
TM
– 93HC46: 3MHz
s
Low power CMOS technology
s
1.8 to 6.0 volt operation
s
Selectable x8 or x16 memory organization
s
Self-timed write cycle with auto-clear
s
Sequential Read
s
Power-up inadvertent write protection
s
1,000,000 program/erase cycles
s
100 year data retention
s
Commercial, industrial and automotive
temperature ranges
s
8-Lead PDIP, SOIC, MSOP and TSSOP
Packages
DESCRIPTION
The CAT93HC46 is a 1K-bit Serial EEPROM memory
devices which is configured as either registers of 16 bits
(ORG pin at V
CC
) or 8 bits (ORG pin at GND). Each
register can be written (or read) serially by using the DI
(or DO) pin. The CAT93HC46 is manufactured using
Catalyst’s advanced CMOS EEPROM floating gate
technology. The device is designed to endure 1,000,000
program/erase cycles and has a data retention of 100
years. The CAT93HC46 is available in 8-pin DIP, 8-pin
SOIC or 8-pin TSSOP packages.
PIN CONFIGURATION
DIP Package (P, L) SOIC Package (J, W) SOIC Package (S, V) MSOP Package (R, Z)
CS
SK
DI
DO
1
2
3
4
8
7
6
5
VCC
NC
ORG
GND
NC
VCC
CS
SK
1
2
3
4
8
7
6
5
ORG
GND
DO
DI
CS
SK
DI
DO
1
2
3
4
8
7
6
5
VCC
NC
ORG
GND
CS
SK
DI
DO
1
2
3
4
8
7
6
5
VCC
NC
ORG
GND
TSSOP Package (U, Y)
CS
SK
DI
DO
1
2
3
4
8
7
6
5
VCC
NC
ORG
GND
PIN FUNCTIONS
Pin Name
CS
SK
DI
DO
V
CC
GND
ORG
NC
PE*
Function
Chip Select
Clock Input
Serial Data Input
Serial Data Output
+1.8 to 6.0V Power Supply
Ground
Memory Organization
No Connection
Program Enable
BLOCK DIAGRAM
VCC
GND
ORG
MEMORY ARRAY
ORGANIZATION
ADDRESS
DECODER
DATA
REGISTER
DI
CS
MODE DECODE
LOGIC
OUTPUT
BUFFER
Note: When the ORG pin is connected to VCC, the X16
organization is selected. When it is connected to ground,
the X8 pin is selected. If the ORG pin is left unconnected,
then an internal pullup device will select the X16
organization.
© 2003 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
SK
CLOCK
GENERATOR
DO
93C46/56/57/66/86 F02
1
Doc. No. 1008,Rev. D
CAT93HC46
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature ....................... –65°C to +150°C
Voltage on any Pin with
Respect to Ground
(1)
............ –2.0V to +V
CC
+2.0V
V
CC
with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (T
A
= 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current
(2)
........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol
N
END(3)
T
DR(3)
V
ZAP(3)
I
LTH(3)(4)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-Up
Min.
1,000,000
100
2000
100
Max.
Units
Cycles/Byte
Years
Volts
mA
Reference Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
D.C. OPERATING CHARACTERISTICS
(Over recommended operating conditions, unless otherwise specified.)
Limits
Symbol
I
CC1
I
CC2
I
SB1
I
SB2(5)
I
LI
I
LO
V
IL1
V
IH1
V
IL2
V
IH2
V
OL1
V
OH1
V
OL2
V
OH2
Parameter
Power Supply Current
(Operating Write)
Power Supply Current
(Operating Read)
Power Supply Current
(Standby) (x8 Mode)
Power Supply Current
(Standby) (x16Mode)
Input Leakage Current
(Including ORG pin)
Output Leakage Current
(Including ORG pin)
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
V
CC
-0.2
2.4
0.2
-0.1
2
0
V
CC
x 0.7
Min.
Typ.
Max.
3
500
10
0
1
1
0.8
V
CC
+ 1
V
CC
x 0.2
V
CC
+ 1
0.4
Units
mA
µA
µA
µA
µA
µA
Test Conditions
f
SK
= 3MHz
V
CC
= 5.0V
f
SK
= 3MHz
V
CC
= 5.0V
CS = 0V
ORG=GND
CS=0V
ORG=Float or V
CC
V
IN
= 0V to V
CC
V
OUT
= 0V to V
CC
,
CS = 0V
4.5V
≤
V
CC
< 5.5V
4.5V
≤
V
CC
< 5.5V
1.8V
≤
V
CC
< 4.5V
1.8V
≤
V
CC
< 4.5V
4.5V
≤
V
CC
< 5.5V,
I
OL
=2.1mA
4.5V
≤
V
CC
< 5.5V,
I
OH
= -400mA
1.8V
≤
V
CC
< 4.5V, I
OL
=1mA
V
V
V
V
V
V
V
1.8V
≤
V
CC
< 4.5V,
I
OH
= -100µA
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+0.5V, which may overshoot to V
CC
+2.0V for periods of less than 20 ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V
CC
+1V.
(5) Standby Current (ISB
2
)=0µA (<900nA).
Doc. No. 1008, Rev. D
2
CAT93HC46
RECOMMENDED OPERATING CONDITIONS
Temperature
Commercial
Industrial
Automotive
Extended
Minimum
0˚C
-40˚C
-40˚C
-40˚C
Maximum
+70˚C
+85˚C
+105˚C
+125˚C
Device
CAT93HC46
CAT93HC46-1.8
Supply Voltage Range
2.5V to 6.0V
1.8V to 6.0V
PIN CAPACITANCE
Symbol
C
OUT(1)
C
IN(1)
Test
OUTPUT CAPACITANCE (DO)
INPUT CAPACITANCE (CS, SK, DI, ORG)
Max.
5
5
Units
pF
pF
Conditions
V
OUT
=0V, T
A
=25˚C,
f
SK
=1MHz
V
IN
=0V, T
A
=25˚C, f
SK
=1MHz
INSTRUCTION SET
Instruction
READ
ERASE
WRITE
EWEN
EWDS
ERAL
WRAL
Start
Bit Opcode
1
1
1
1
1
1
1
10
11
01
00
00
00
00
Address
x8
x16
A6-A0
A6-A0
A6-A0
11XXXXX
00XXXXX
10XXXXX
01XXXXX
Data
x8
x16
Comments
Read Address AN–A0
Clear Address AN–A0
D7-D0
D15-D0 Write Address AN–A0
Write Enable
Write Disable
Clear All Addresses
D7-D0
D15-D0 Write All Addresses
A5-A0
A5-A0
A5-A0
11XXXX
00XXXX
10XXXX
01XXXX
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
3
Doc. No. 1008, Rev. D
CAT93HC46
POWER-UP TIMING
(1)(2)
SYMBOL
t
PUR
t
PUW
PARAMETER
Power-up to Read Operation
Power-up to Write Operation
Max
1
1
Units
ms
ms
A.C. CHARACTERISTICS
Limits
V
CC
=
1.8V-6V
SYMBOL PARAMETER
t
CSS
t
CSH
t
DIS
t
DIH
t
PD1
t
PD0
t
HZ(1)
t
EW
t
CSMIN
t
SKHI
t
SKLOW
t
SV
SK
MAX
CS Setup Time
CS Hold Time
DI Setup Time
DI Hold Time
Output Delay to 1
Output Delay to 0
Output Delay to High-Z
Program/Erase Pulse Width
Minimum CS Low Time
Minimum SK High Time
Minimum SK Low Time
Output Delay to Status Valid
Maximum Clock Frequency
DC
1
1
1
1
250
DC
Min.
200
0
400
400
1
1
400
5
0.5
0.5
0.5
0.5
1000
DC
Max.
V
CC
=
2.5V-6V
Min.
100
0
200
200
0.5
0.5
200
5
0.1
0.1
0.1
0.1
3000
Max.
V
CC
=
4.5V-5.5V
Min.
50
0
50
50
0.1
0.1
100
5
Max.
UNITS
ns
ns
ns
ns
µs
µs
ns
ms
µs
µs
µs
µs
kHz
C
L
= 100pF
V
IL
= 0.45V
V
IH
= 2.4V
C
L
= 100pF
V
OL
==100pF
0.8V
C
L
V
OH
(3)
= 2.0v
Test
Conditions
NOTE:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
(3) The input levels and timing reference points are shown in “AC Test Conditions” table.
A.C. TEST CONDITIONS
Input Rise and Fall Times
Input Pulse Voltages
Timing Reference Voltages
Input Pulse Voltages
Timing Reference Voltages
≤
50ns
0.4V to 2.4V
0.8V, 2.0V
0.2V
CC
to 0.7V
CC
0.5V
CC
4.5V
≤
V
CC
≤
5.5V
4.5V
≤
V
CC
≤
5.5V
1.8V
≤
V
CC
≤
4.5V
1.8V
≤
V
CC
≤
4.5V
Doc. No. 1008, Rev. D
4
CAT93HC46
DEVICE OPERATION
The CAT93HC46 is a 1024-bit nonvolatile memory
intended for use with industry standard microprocessors.
The CAT93HC46 can be organized as either registers of
16 bits or 8 bits. When organized as X16, seven 9-bit
instructions control the reading, writing and erase
operations of the device. When organized as X8, seven
10-bit instructions control the reading, writing and erase
operations of the device. The CAT93HC46 operates on
a single power supply and will generate on chip, the high
voltage required during any write operation.
Instructions, addresses, and write data are clocked into
the DI pin on the rising edge of the clock (SK). The DO
pin is normally in a high impedance state except when
reading data from the device, or when checking the
ready/busy status after a write operation.
The ready/busy status can be determined after the start
of a write operation by selecting the device (CS high) and
polling the DO pin; DO low indicates that the write
operation is not completed, while DO high indicates that
the device is ready for the next instruction. If necessary,
the DO pin may be placed back into a high impedance
state during chip select by shifting a dummy “1” into the
DI pin. The DO pin will enter the high impedance state on
the falling edge of the clock (SK). Placing the DO pin into
the high impedance state is recommended in applications
where the DI pin and the DO pin are to be tied together
to form a common DI/O pin.
Figure 1. Sychronous Data Timing
tSKHI
SK
tDIS
DI
tCSS
CS
tDIS
DO
tPD0,tPD1
DATA VALID
tCSMIN
VALID
VALID
tDIH
tSKLOW
tCSH
Figure 2a. Read Instruction Timing
SK
tCS MIN
CS
STANDBY
AN
DI
1
1
0
tHZ
0
DN
DN—
1
D1
D0
HIGH-Z
AN—1
A0
DO
HIGH-Z
tPD0
5
Doc. No. 1008, Rev. D
51单片机
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