TS88915T
Low Skew CMOS PLL Clock Driver Tri-State
70 and 100 MHz Versions
Datasheet
Features
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•
•
•
•
Vcc = 5V ± 5%
Military Temperature Range
Fully Compatible with the TS68040
Five Low Skew Outputs
– Five Outputs (Q0-Q4) with Output-to-Output Skew < 500 ps Each Being Phase End Frequency Locked to the SYNC Input
Three Additional Outputs are Available:
– The 2X_Q Output Runs Twice the System “Q” Frequency
– The Q/2 Output Runs At 1/2 the System “Q” Frequency
– The Q5 Output is Inverted (180° Phase Shift)
Two Selectable Clock Inputs
– Two Selectable CLOCK Inputs are Available for Test or Redundancy Purposes
– Test Mode Pin (PLL_EN) Provided for Low Frequency Testing
– All Outputs Can Go Into High Impedance (3-state) for Board Test Purposes
Input Frequency Range From 5 MHz to 2X_Q FMAX
Three Input/Output Ratios
– Input/Output Phase-locked Frequency Ratios of 1:2, 1:1 and 2:1 are Available
Low Part-to-part Skew
– The Phase Variation from Part-to-part Between the SYNC and FEEDBACK Inputs is Less than 550 ps (Derived From the
tPD Specification, which Defines the Part-to-part Skew)
CMOS and TTL Compatible
– All Outputs Can Drive Either CMOS or TTL Inputs
– All Inputs are TTL-level Compatible
LOCK Indicator (LOCK) Indicates a Phase-locked State
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Description
The TS88915T Clock Driver utilizes a phazed-locked loop (PLL) technology to lock its low skew outputs’ frequency and
phase onto an input reference clock. It is designed to provide clock distribution for high performance microprocessors such
as TS68040, TSPC603E,TSPC603P,TSPC603R, PCI bridge, RAM’s, MMU’s.
Screening/Quality
This Product is Manufactured:
• Based Upon the Generic Flow of MIL-STD-883
• or According to e2v-Grenoble Standard
R suffix
PGA 29
Ceramic Pin Grid Array
W suffix
LDCC 28
Leaded Ceramic Chip Carrier
Visit our website: www.e2v.com
for the latest version of the datasheet
e2v semiconductors SAS 2007
0854B–HIREL–07/07
TS88915T
1. Introduction
The TS88915T is a CMOS PLL Clock Driver using phase-locked loop (PLL) technology. The PLL allows
the high current and low skew outputs to lock onto a single input and distribute it with essentially zero
delay to multiple components on a board. The PLL also allows the TS88915T to multiply a low frequency
input clock and distribute it locally at a higher (2X) system frequency. Multiple 88915’s can lock onto a
single reference clock, which is ideal for applications when a central system clock must be distributed
synchronously to multiple boards (see
Figure 7-8 on page 15).
Figure 1-1.
TS88915T Block Diagram (All Versions)
SYNC[0]
LOCK
0
M
U
X
PHASE/FREQ.
DETECTOR
CHARGE PUMP/
LOOP FILTER
VOLTAGE
CONTROLLED
OSCILLATOR
FEEDBACK
SYNC[1]
1
REF_SEL
EXT. REC NETWORK
(RC1 pin)
0
PLL_EN
MUX
1
2X_Q
D
(÷1)
1
M
U
X
D
CP
FREQ_SEL
R
CP
R
Q
Q
Q0
DIVIDE
BY TWO
(÷2)
0
Q
Q
Q1
OE/RST
D
CP
R
Q
Q
Q2
D
CP
R
Q
Q
Q3
D
CP
R
Q
Q
Q4
D
CP
R
Q
Q
Q5
D
CP
R
Q
Q
Q/2
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0854B–HIREL–07/07
e2v semiconductors SAS 2007
TS88915T
2. Pin Assignments
2.1
29-lead Pin Grid Array (PGA)
Figure 2-1.
29-lead PGA (Bottom View)
F
F/SL
E
GNDA
D
VCCA
C
SYC0
B
FDBK
A
NC
VCC
GND
Q4
Q*2
RST
Q5
VCC
Q/2
GND
R/SL
Q3
VCC
RC1
TS88915T
(BOTTOM VIEW)
GND
Q2
SYC1
GND
Q1
P/EN
LOCK
Q0
VCC
GND
1
2
3
4
5
6
2.2
28-lead Ceramic Leaded Chip Carrier (LDCC)
Figure 2-2.
28-lead LDCC (Top View)
OE/RST VCC Q5 GND Q4
4
3
2
1
28
VCC 2X_Q
27
26 25
24
23
TS88915T
(TOP VIEW)
22
21
20
19
12
13
14
15
16
17
18
FEEDBACK
REF_SEL
SYNC[0]
VCC (AN)
RC1
GND (AN)
SYNC[1]
5
6
7
8
9
10
11
Q/2
GND
Q3
VCC
Q2
GND
LOCK
FREQ_SEL GND Q0 VCC
Q1 GND PLL_EN
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0854B–HIREL–07/07
e2v semiconductors SAS 2007
TS88915T
3. Signal Description
Table 3-1.
Pin Name
SYNC[0]
SYNC[1]
REF_SEL
FREQ_SEL
FEEDBACK
RC1
Q(0-4)
Q5
2x_Q
Q/2
LOCK
OE/RST
PLL_EN
VCC, GND
Signal Index
Num
1
1
1
1
1
1
5
1
1
1
1
1
1
11
I/O
Input
Input
Input
Input
Input
Input
Output
Output
Output
Output
Output
Input
Input
Power
Signal Function
Reference Clock Input
Reference Clock Input
Chooses Reference Between SYNC[0] and SYNC[1]
Doubles VCO Internal Frequency
Feedback Input to Phase Detector
Input for External RC Network
Clock Output (Locked to SYNC)
Inverse of Clock Output
2 x Clock Output (Q) Frequency (Synchronous)
Clock Output (Q) Frequency ÷ 2 (Synchronous)
Indicates Phase Lock has been Achieved (High when Locked)
Output Enable/Asynchronous Reset (Active Low)
Disables Phase-lock for Low Frequency Testing
Power and Ground pins
Pins 8 and 10 are “analog” supply pins for internal PLL only
4. Scope
This drawing describes the specific requirements for the clock driver TS88915T, in compliance with
MIL-STD-883 class B or e2v standard screening.
5. Applicable Documents
1. MIL-STD-883: Test methods and procedures for electronics.
2. MIL-PRF-38535 appendix A: General specifications for microcircuits.
The microcircuits are in accordance with the applicable documents and as specified herein.
5.1
5.1.1
Design and Construction
Terminal Connections
Depending on the package, the terminal connections shall be as shown in
Figure 2-1
and
Figure 2-2.
Lead Material and Finish
Lead material and finish shall be as specified in MIL-STD-1835 (see
Section 10. on page 17).
Package
The macrocircuits are packaged in hermetically sealed ceramic packages, which conform to case out-
lines of MIL-STD-1835, but
“Package Mechanical Data” on page 17.
The precise case outlines are described at the end of the specification (see
“Package Mechanical Data”
on page 178)
and into MIL-STD-1835.
5.1.2
5.1.3
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TS88915T
5.2
Absolute Maximum Ratings
Stresses above the absolute maximum rating may cause permanent damage to the device. Extended
operation at the maximum levels may degrade performance and affect reliability.
Table 5-1.
Parameter
Supply Voltage
Input Voltage
Storage Temperature Range
Power Dissipation
PGA Package
LDCC Package
Thermal Resistance Junction-Case
PGA29
LDCC28
Note:
Absolute Maximum Rating for the TS88915T
Symbol
V
CC
V
in
T
stg
P
D
Min
-0.5
-0.5
-65
Max
6.0
V
CC
+ 0.5
+150
500
Unit
V
V
°C
mW
Θ
JC
-
-
7
7
°C/W
Functional operating conditions are given in AC and DC electrical specifications. Stresses beyond the
absolute maximums listed may affect device reliability or cause permanent damage to the device.
Caution:
Input voltage must not be greater than the supply voltage by more than 2.5V at all times including
during power-on reset.
5.3
Mechanical and Environment
The microcircuits shall meet all environmental requirements of either MIL-STD-883 for class B devices or
for e2v standard screening.
5.4
Marking
The document that defines the markings is identified in the related reference documents. Each microcir-
cuit is legible and permanently marked with the following information as minimum:
• e2v Logo
• Manufacturer’s Part Number
• Class B Identification
• Date-code of Inspection Lot
• ESD Identifier If Available
• Country of Manufacturing
6. Electrical Characteristics
6.1
General Requirements
All static and dynamic electrical characteristics specified for inspection purposes and the relevant mea-
surement conditions are given below:
• Table Static Electrical Characteristics for the Electrical Variants
• Table Dynamic Electrical Characteristics for TS88915T (70 MHz and 100 MHz Versions)
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0854B–HIREL–07/07
e2v semiconductors SAS 2007
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