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5962-8867004KX

产品描述OT PLD, 20ns, CMOS, CDFP24, GLASS SEALED, CERPACK-24
产品类别可编程逻辑器件    可编程逻辑   
文件大小71KB,共3页
制造商Cypress(赛普拉斯)
下载文档 详细参数 选型对比 全文预览

5962-8867004KX概述

OT PLD, 20ns, CMOS, CDFP24, GLASS SEALED, CERPACK-24

5962-8867004KX规格参数

参数名称属性值
零件包装代码DFP
包装说明DFP,
针数24
Reach Compliance Codeunknown
ECCN代码3A001.A.2.C
其他特性10 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK; VARIABLE PRODUCT TERMS
最大时钟频率31.2 MHz
JESD-30 代码R-GDFP-F24
长度15.367 mm
专用输入次数11
I/O 线路数量10
端子数量24
最高工作温度125 °C
最低工作温度-55 °C
组织11 DEDICATED INPUTS, 10 I/O
输出函数MACROCELL
封装主体材料CERAMIC, GLASS-SEALED
封装代码DFP
封装形状RECTANGULAR
封装形式FLATPACK
可编程逻辑类型OT PLD
传播延迟20 ns
认证状态Not Qualified
座面最大高度2.286 mm
最大供电电压5.5 V
最小供电电压4.5 V
标称供电电压5 V
表面贴装YES
技术CMOS
温度等级MILITARY
端子形式FLAT
端子节距1.27 mm
端子位置DUAL
宽度9.652 mm
Base Number Matches1

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This is an abbreviated datasheet. Contact a Cypress repre-
sentative for complete specifications. For new designs,
please refer to the PALCE22V10
PALC22V10B
Reprogrammable CMOS PAL® Device
Features
• Advanced second generation PAL architecture
• Low power
— 90 mA max. standard
— 100 mA max. military
• CMOS EPROM technology for reprogrammability
• Variable product terms
— 2 x (8 through 16) product terms
• User-programmable macrocell
— Output polarity control
— Individually selectable for registered or combinato-
rial operation
— 15 ns commercial and industrial
10 ns t
CO
10 ns t
S
15 ns t
PD
50 MHz
— 15 ns and “20 ns” military
10/15 ns t
CO
10/17 ns t
S
15/20 ns t
PD
50/31 MHz
• Up to 22 input terms and 10 outputs
• Enhanced test features
— Phantom array
— Top test
— Bottom test
— Preload
• High reliability
— Proven EPROM technology
— 100% programming and functional testing
• Windowed DIP, windowed LCC, DIP, LCC, PLCC avail-
able
Functional Description
The Cypress PALC22V10B is a CMOS second-generation
programmable logic array device. It is implemented with the
familiar sum-of-products (AND-OR) logic structure and a new
concept, the “Programmable Macrocell.”
The PALC22V10B is executed in a 24-pin 300-mil molded DIP,
a 300-mil windowed cerDIP, a 28-lead square ceramic lead-
less chip carrier, a 28-lead square plastic leaded chip carrier,
and provides up to 22 inputs and 10 outputs. When the win-
dowed cerDIP is exposed to UV light, the 22V10B is erased
and can then be reprogrammed. The programmable macrocell
provides the capability of defining the architecture of each out-
put individually. Each of the 10 potential outputs may be spec-
ified as “registered” or “combinatorial.” Polarity of each output
may also be individually
Logic Block Diagram (PDIP/CDIP)
V
SS
12
I
11
I
10
I
9
I
8
I
7
I
6
I
5
I
4
I
3
I
2
CP/I
1
PROGRAMMABLE
ANDARRAY
(132X 44)
8
10
12
14
16
16
14
12
10
8
Reset
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Preset
13
I
14
I/O9
15
I/O8
16
I/O7
17
I/O6
18
I/O5
19
I/O4
20
I/O3
21
I/O2
22
I/O1
23
I/O0
24
V
CC
V10B–1
Cypress Semiconductor Corporation
Document #: 38-03018 Rev. **
3901 North First Street
San Jose
CA 95134 • 408-943-2600
Revised March 6, 1997

5962-8867004KX相似产品对比

5962-8867004KX PALC22V10B-15JCT PALC22V10B-15JIT
描述 OT PLD, 20ns, CMOS, CDFP24, GLASS SEALED, CERPACK-24 OT PLD, 15ns, CMOS, PQCC28, PLASTIC, LCC-28 OT PLD, 15ns, CMOS, PQCC28, PLASTIC, LCC-28
零件包装代码 DFP QLCC QLCC
包装说明 DFP, QCCJ, QCCJ,
针数 24 28 28
Reach Compliance Code unknown unknown unknown
其他特性 10 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK; VARIABLE PRODUCT TERMS 10 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK; VARIABLE PRODUCT TERMS 10 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK; VARIABLE PRODUCT TERMS
最大时钟频率 31.2 MHz 50 MHz 50 MHz
JESD-30 代码 R-GDFP-F24 S-PQCC-J28 S-PQCC-J28
长度 15.367 mm 11.5316 mm 11.5316 mm
专用输入次数 11 11 11
I/O 线路数量 10 10 10
端子数量 24 28 28
最高工作温度 125 °C 75 °C 85 °C
最低工作温度 -55 °C - -40 °C
组织 11 DEDICATED INPUTS, 10 I/O 11 DEDICATED INPUTS, 10 I/O 11 DEDICATED INPUTS, 10 I/O
输出函数 MACROCELL MACROCELL MACROCELL
封装主体材料 CERAMIC, GLASS-SEALED PLASTIC/EPOXY PLASTIC/EPOXY
封装代码 DFP QCCJ QCCJ
封装形状 RECTANGULAR SQUARE SQUARE
封装形式 FLATPACK CHIP CARRIER CHIP CARRIER
可编程逻辑类型 OT PLD OT PLD OT PLD
传播延迟 20 ns 15 ns 15 ns
认证状态 Not Qualified Not Qualified Not Qualified
座面最大高度 2.286 mm 4.572 mm 4.572 mm
最大供电电压 5.5 V 5.5 V 5.5 V
最小供电电压 4.5 V 4.5 V 4.5 V
标称供电电压 5 V 5 V 5 V
表面贴装 YES YES YES
技术 CMOS CMOS CMOS
温度等级 MILITARY COMMERCIAL EXTENDED INDUSTRIAL
端子形式 FLAT J BEND J BEND
端子节距 1.27 mm 1.27 mm 1.27 mm
端子位置 DUAL QUAD QUAD
宽度 9.652 mm 11.5316 mm 11.5316 mm
厂商名称 - Cypress(赛普拉斯) Cypress(赛普拉斯)

 
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