74ALVC16838 Low Voltage 16-Bit Selectable Register/Buffer with 3.6V Tolerant Inputs and Outputs
December 2001
Revised December 2001
74ALVC16838
Low Voltage 16-Bit Selectable Register/Buffer
with 3.6V Tolerant Inputs and Outputs
General Description
The ALVC16838 contains sixteen non-inverting selectable
buffered or registered paths. The device can be configured
to operate in a registered, or flow through buffer mode by
utilizing the register enable (REGE) and Clock (CLK) sig-
nals. The device operates in a 16-bit word wide mode. All
outputs can be placed into 3-State through use of the OE
Pin. These devices are ideally suited for buffered or regis-
tered 168 pin and 200 pin SDRAM DIMM memory mod-
ules.
The 74ALVC16838 is designed for low voltage (1.65V to
3.6V) V
CC
applications with I/O compatibility up to 3.6V.
The 74ALVC16838 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
s
Compatible with PC100 and PC133 DIMM module
specifications
s
1.65V to 3.6V V
CC
supply operation
s
3.6V tolerant inputs and outputs
s
t
PD
(CLK to O
n
)
3.5 ns max for 3.0V to 3.6V V
CC
4.5 ns max for 2.3V to 2.7V V
CC
8.0 ns max for 1.65V to 1.95V V
CC
s
Power-off high impedance inputs and outputs
s
Supports live insertion and withdrawal (Note 1)
s
Uses patented noise/EMI reduction circuitry
s
Ideal for SDRAM DIMM modules
s
Latchup conforms to JEDEC JED78
s
ESD performance:
Human body model
>
2000V
Machine model
>
200V
Note 1:
To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Order Number
74ALVC16838MTD
Package Number
MTD48
Package Description
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
OE
I
0
–I
15
O
0
–O
15
CLK
REGE
Description
Output Enable Input (Active LOW)
Inputs
Outputs
Clock Input
Register Enable Input
© 2001 Fairchild Semiconductor Corporation
DS500714
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74ALVC16838
Connection Diagram
Truth Table
Inputs
CLK
REGE
H
H
L
L
X
I
n
H
L
H
L
X
OE
L
L
L
L
H
Outputs
O
n
H
L
H
L
Z
↑
↑
X
X
X
H
=
Logic HIGH
L
=
Logic LOW
X
=
Don’t Care, but not floating
Z
=
High Impedance
↑ =
LOW-to-HIGH Clock Transition
Functional Description
The 74ALVC16838 consists of sixteen selectable non-
inverting buffers or registers with word wide modes. Mode
functionality is selected through operation of the CLK and
REGE pin as shown by the truth table. When REGE is held
at a logic HIGH the device operates as a 16-bit register.
Data is transferred from I
n
to O
n
on the rising edge of the
CLK input. When the REGE pin is held at a logic LOW the
device operates in a flow through mode and data propa-
gates directly from the I to the O outputs. All outputs can be
3-STATE by holding the OE pin at a logic HIGH.
Logic Diagram
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2
74ALVC16838
Absolute Maximum Ratings
(Note 2)
Supply Voltage (V
CC
)
DC Input Voltage (V
I
)
Output Voltage (V
O
) (Note 3)
DC Input Diode Current (I
IK
)
V
I
<
0V
DC Output Diode Current (I
OK
)
V
O
<
0V
DC Output Source/Sink Current
(I
OH
/I
OL
)
DC V
CC
or GND Current per
Supply Pin (I
CC
or GND)
Storage Temperature Range (T
STG
)
−
0.5V to
+
4.6V
−
0.5V to 4.6V
−
0.5V to V
CC
+
0.5V
−
50 mA
−
50 mA
±
50 mA
±
100 mA
−
65
°
C to
+
150
°
C
Recommended Operating
Conditions
(Note 4)
Power Supply
Operating
Input Voltage (V
I
)
Output Voltage (V
O
)
Free Air Operating Temperature (T
A
)
Minimum Input Edge Rate (
∆
t/
∆
V)
V
IN
=
0.8V to 2.0V, V
CC
=
3.0V
10 ns/V
Note 2:
The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the Absolute Maximum Rat-
ings. The “Recommended Operating Conditions” table will define the condi-
tions for actual device operation.
Note 3:
I
O
Absolute Maximum Rating must be observed.
Note 4:
Floating or unused inputs must be held HIGH or LOW.
1.65V to 3.6V
0V to V
CC
0V to V
CC
−
40
°
C to
+
85
°
C
DC Electrical Characteristics
Symbol
V
IH
Parameter
HIGH Level Input Voltage
Conditions
V
CC
(V)
1.65 -1.95
2.3 - 2.7
2.7 - 3.6
V
IL
LOW Level Input Voltage
1.65 -1.95
2.3 - 2.7
2.7 - 3.6
V
OH
HIGH Level Output Voltage
I
OH
= −100 µA
I
OH
= −4
mA
I
OH
= −6
mA
I
OH
= −12
mA
1.65 - 3.6
1.65
2.3
2.3
2.7
3.0
I
OH
= −24
mA
V
OL
LOW Level Output Voltage
I
OL
=
100
µA
I
OL
=
4 mA
I
OL
=
6 mA
I
OL
=
12mA
I
OL
=
24 mA
I
I
I
OZ
I
CC
∆I
CC
Input Leakage Current
3-STATE Output Leakage
Quiescent Supply Current
Increase in I
CC
per Input
0
≤
V
I
≤
3.6V
0
≤
V
O
≤
3.6V
V
I
=
V
CC
or GND, I
O
=
0
V
IH
=
V
CC
−
0.6V
3.0
1.65 - 3.6
1.65
2.3
2.3
2.7
3
3.6
3.6
3.6
3 -3.6
V
CC
- 0.2
1.2
2
1.7
2.2
2.4
2
0.2
0.45
0.4
0.7
0.4
0.55
±5.0
±10
40
750
µA
µA
µA
µA
V
V
Min
0.65 x V
CC
1.7
2.0
0.35 x V
CC
0.7
0.8
V
V
Max
Units
3
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74ALVC16838
AC Electrical Characteristics
T
A
= −40°C
to
+85°C,
R
L
=
500Ω
Symbol
Parameter
C
L
=
50 pF
V
CC
=
3.3V
±
0.3V
Min
f
MAX
t
PHL
, t
PLH
t
PHL
, t
PLH
t
PHL
, t
PLH
t
PZL
, t
PZH
t
PLZ
, t
PHZ
t
W
t
S
t
H
Maximum Clock Frequency
Propagation Delay
Bus to Bus (REGE
=
0)
Propagation Delay
CLK to Bus (REGE
=
1)
Propagation Delay
REGE to Bus
Output Enable Time
Output Disable Time
Pulse Width
Setup Time
Hold Time
250
1.3
1.3
1.3
1.3
1.3
1.5
1.0
0.7
3.0
3.5
3.5
4.0
4.0
Max
V
CC
=
2.7V
Min
200
1.5
1.5
1.5
1.5
1.5
1.5
1.0
0.7
4.0
4.5
4.5
5.2
4.4
Max
C
L
=
30 pF
V
CC
=
2.5V
±
0.2V
Min
200
1.0
1.0
1.0
1.0
1.0
1.5
1.0
0.7
3.5
4.0
4.0
4.7
3.9
Max
V
CC
=
1.8V
±
0.15V
Min
100
1.5
1.5
1.5
1.5
1.5
4.0
2.5
1.0
7.0
8.0
8.0
9.4
7.0
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
Capacitance
Symbol
C
IN
C
OUT
C
PD
Input Capacitance
Output Capacitance
Power Dissipation Capacitance
Parameter
V
I
=
0V or V
CC
V
I
=
0V or V
CC
Outputs Enabled f
=
10 MHz, C
L
=
50 pF
Conditions
T
A
= +25°C
V
CC
3.3
3.3
3.3
2.5
Typical
6
7
20
20
Units
pF
pF
pF
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4
74ALVC16838
AC Loading and Waveforms
TABLE 1. Values for Figure 1
TEST
t
PLH
, t
PHL
t
PZL
, t
PLZ
t
PZH
, t
PHZ
SWITCH
Open
V
L
GND
FIGURE 1. AC Test Circuit
TABLE 2. Variable Matrix
(Input Characteristics: f
=
1MHz; t
r
=
t
f
=
2ns; Z
0
=
50
Ω
Symbol
V
mi
V
mo
V
X
V
Y
V
L
V
CC
3.3V
±
0.3V
1.5V
1.5V
V
OL
+
0.3V
V
OH
−
0.3V
6V
2.7V
1.5V
1.5V
V
OL
+
0.3V
V
OH
−
0.3V
6V
2.5V
±
0.2V
V
CC
/2
V
CC
/2
V
OL
+
0.15V
V
OH
−
0.15V
V
CC
*2
1.8V
±
0.15V
V
CC
/2
V
CC
/2
V
OL
+
0.15V
V
OH
−
0.15V
V
CC
*2
FIGURE 2. Waveform for Inverting and Non-Inverting
Functions
FIGURE 3. 3-STATE Output High Enable and Disable
Times for Low Voltage Logic
FIGURE 4. Propagation Delay, Pulse Width and t
rec
Waveforms
FIGURE 5. Setup Time, Hold Time and Recovery Time
for Low Voltage Logic
5
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