RD151TS3315ARP, RD151TS3325ARP
Spread Spectrum Clock for EMI Solution
REJ03D0796-0100
Rev.1.00
May 11, 2006
Description
RD151TS3315ARP and RD151TS3325ARP is a high-performance Spread Spectrum Clock generator. It is suitable for
EMI solution of electric systems.
Features
•
Supports 20 MHz to 40 MHz operations. Multiple rate (XIN: SSCOUT) = 1: 4
Input frequency 80 MHz to 160 MHz
•
Spread spectrum modulation ; RD151TS3315ARP :
±1.5%, ±0.5%
(Central spread modulation)
RD151TS3325ARP : –3.0%, –1.0% (Down spread modulation)
Key Specifications
•
•
•
•
•
Supply voltages: V
DD
= 3.3 V ±0.3 V
Cycle to cycle jitter =
±100
ps typ.
Clock output duty cycle = 50 ±5%
Output slew rate = 0.7 V/ns typ.
Ordering Information
Part Name
Package Type
SOP-8 pin
(JEDEC)
Package Code
(Previous Code)
PRSP0008DD-C
(FP-8DCV)
RP
Package
Abbreviation
Taping Abbreviation
(Quantity)
H (2,500 pcs / Reel)
RD151TS3315ARPH0
RD151TS3325ARPH0
Block Diagram
VDD
GND
NC
XIN
1/M
R = 1 MΩ
XOUT
OSC
Synthesizer
1/N
SSC Modulator
SSCOUT
SEL
R = 350 kΩ
SSN
Mode Control
R = 350 kΩ
Rev.1.00 May 11, 2006 page 1 of 8
RD151TS3315ARP, RD151TS3325ARP
Pin Arrangement
XIN
1
8
VDD
XOUT
2
7
SEL
NC
3
6
SSCOUT
SSN
4
5
GND
(Top view)
Pin Descriptions
Pin name
GND
VDD
NC
SSCOUT
XIN
XOUT
SEL
SSN
No.
5
8
3
6
1
2
7
4
Type
Ground
Power
NC
Output
Input
Output
Input
Input
Description
GND pin
Power supply pin.
Don’t connect any VDD or GND.
Spread spectrum modulated clock output.
Oscillator input.
Oscillator output.
SSC% mode select pin. LVCMOS level input.
Pull-down by internal resistor (350 kΩ).
SSC ON/OFF select pin. LVCMOS level input.
Pull–down by internal resistor (350 kΩ).
SSC Function Table
STB
0
0
1
1
Note:
SEL
0
1
0
1
RD151TS3315ARP(Central spread)
±1.5%*
1
±0.5%
OFF
RD151TS3325ARP(Down spread)
–3.0%*
1
–1.0%
OFF
1.
±1.5%(TS3315ARP)
/ -3.0%(TS3325ARP) SSC is selected for default by internal pull-down resistors.
Clock Frequency Table
PRODUCT
RD151TS3315ARP
RD151TS3325ARP
XIN(MHz)
20 to 40
20 to 40
SSCOUT(MHz)
80 to 160
80 to 160
Multiply rate (XIN: SSCOUT)
1:4
1:4
Rev.1.00 May 11, 2006 page 2 of 8
RD151TS3315ARP, RD151TS3325ARP
Absolute Maximum Ratings
Item
Supply voltage
Input voltage
Output voltage
*1
Input clamp current
Output clamp current
Continuous output current
Maximum power dissipation
Storage temperature
Symbol
V
DD
V
I
V
O
I
IK
I
OK
I
O
T
stg
Ratings
–0.5 to 4.6
–0.5 to 4.6
–0.5 to V
DD
+0.5
–50
–50
±50
0.7
–65 to +150
Unit
V
V
V
mA
mA
mA
W
°
C
Conditions
V
I
< 0
V
O
< 0
V
O
= 0 to V
DD
Ta = 55
°
C (in still air)
Notes: Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device.
1. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings
are observed.
Recommended Operating Conditions
Item
Supply voltage
DC input signal voltage
High level input voltage
Low level input voltage
Input clock duty cycle
Operating temperature
Symbol
V
DD
V
IH
V
IL
T
a
Min
3.0
–0.3
0.7×V
DD
–0.3
45
–20
Typ
3.3
—
—
—
50
—
Max
3.6
V
DD
+0.3
V
DD
+0.3
0.3×V
DD
55
85
Unit
V
V
V
V
%
°C
Conditions
DC Electrical Characteristics
Ta = –20 to 85 °C, V
DD
= 3.0 to 3.6 V
Item
Input current
Symbol
I
I
Min
—
—
Input capacitance
C
I
—
Typ
—
—
3
Max
±20
±100
—
pF
Unit
µA
Test Conditions
V
I
= 0 V or 3.6 V, V
DD
= 3.6 V,
XIN pin
V
I
= 0 V or 3.6 V, V
DD
= 3.6 V,
SEL, SSN pins
SEL, SSN pins
DC Electrical Characteristics / SSC Clock Output
Ta = –20 to 85 °C, V
DD
= 3.0 to 3.6 V
Item
Output voltage
Output current
Output impedance
Symbol
V
OH
V
OL
I
OH
I
OL
Min
V
DD
–0.2
—
—
—
—
Typ
—
—
–44
44
40
Max
—
200
—
—
—
Unit
V
mV
mA
Ω
Test Conditions
I
OH
= –1 mA
I
OL
= 1 mA
V
OH
= 1.5 V, V
DD
= 3.3 V
V
OL
= 1.5 V, V
DD
= 3.3 V
Note: Parameters are target of design. Not 100% tested in production.
Rev.1.00 May 11, 2006 page 3 of 8
RD151TS3315ARP, RD151TS3325ARP
AC Electrical Characteristics / SSC Clock Output
Ta = 25°C, V
DD
= 3.3 V, C
L
= 15 pF
Item
Operating current
Cycle to cycle jitter *
1
Symbol
I
DD
t
CCS
Min
—
—
Typ
24
|100|
Max
30
—
Unit
mA
ps
Test Conditions
V
DD
= 3.3 V, C
L
= 15 pF,
XIN = 40 MHz
SEL = 0, C
L
= 0 pF
SSC =
±1.5%
(TS3315ARP)
SSC = –3.0% (TS3325ARP)
V
DD
= 3.3 V,
0.2
×
V
DD
to 0.8
×
V
DD
Notes
Figure 1
Slew rate
t
SL
—
2.0
5.0
V/ns
Clock duty cycle
45
50
55
%
*2
Stabilization time
—
—
2
ms
Notes: Parameters are target of design. Not 100% tested in production.
1. Cycle to cycle jitter is included spread spectrum modulation.
2. Stabilization time is the time required for the integrated circuit to obtain phase lock of its input signal after
power up.
SSCOUT
tcycle n
tcycle n+1
t
CCS
= (tcycle n)
–
(tcycle n+1)
Figure 1 Cycle to cycle jitter
Rev.1.00 May 11, 2006 page 4 of 8
RD151TS3315ARP, RD151TS3325ARP
Application Information
1. Recommended Circuit Configuration
The power supply circuit of the optimal performance on the application of a system should refer to Figure 2.
VDD decoupling is important to both reduce Jitter and EMI radiation.
The C1 decoupling capacitor should be placed as close to the VDD pin as possible, otherwise the increased trace
inductance will negate its decoupling capability.
XIN
(Crystal or Reference input)
XOUT
(Crystal or Not connection)
NC
1
8
C1
SEL
R1
C2
VDD
2
7
GND GND
3
6
SSCOUT
SSN
4
5
GND
Notes:
C1 = High frequency supply decoupling capacitor.
(0.1
µF
recommended)
C2 = Low frequency supply decoupling capacitor.
(22
µF
recommended)
R1 = Match value to line impedance.
Figure 2 Recommended circuit configuration
Rev.1.00 May 11, 2006 page 5 of 8
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