TRAILING EDGE PRODUCT - MINIMUM ORDER APPLIES
128K x 32 SRAM MODULE
PUMA 68S4000X - 12/15/20/25
Elm Road, West Chirton Industrial Estate, North Shields,
NE29 8SE, ENGLAND. TEL +44 (0191) 2930500. FAX +44 (0191)
2590997
Issue 1.5 : December 1998
Features
• Very Fast Access Times of 12/15/20/25 ns.
• JEDEC 68 'J' leaded plastic surface mount Substrate
• Upgradeable footprint.
• User Configurable as 8 / 16 / 32 bit wide output.
• Operating Power
Low Power Standby
-L Version
• Fully Static operation.
• Multiple ground pins for maximum noise immunity.
• Single 5V±10% Power supply.
(32-BIT)
(TTL)
(CMOS)
4.40 W (Max)
1.32 W (Max)
44 mW (Max)
Description
The PUMA68S4000X is a 4Mbit CMOS High Speed
Static RAM organised as 128K x 32 in a JEDEC 68
pin surface mount PLCC, available with access
times of 15ns, 20ns, or 25ns. The output width is user
configurable as 8 , 16 or 32 bits using four Chip
Selects (CS1~4).
The device features low power standby, multiple
ground pins for maximum noise immunity and TTL
compatible inputs and outputs. The PUMA
68S4000X offers a dramatic space saving
advantage over four standard 128Kx8 devices. A low
power standby option with 2V data retention mode is
available.
Block Diagram
A0-A16
OE
WE
128Kx8
SRAM
CS1
CS2
CS3
CS4
D0-7
D8-15
D16-23
D24-31
128Kx8
SRAM
128Kx8
SRAM
128Kx8
SRAM
Pin Definition
D16
NC
NC
CS4
CS3
CS2
CS1
NC
VCC
NC
NC
OE
WE
A16
A15
A14
D15
9
8
7
6
5
4
3
2
1 68 67 66 65 64 63 62 61
60
59
58
57
56
D17
D18
D19
VSS
D20
D21
D22
D23
VCC
D24
D25
D26
D27
VSS
D28
D29
D30
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
PUMA 68S4000X
VIEW
FROM
ABOVE
55
54
53
52
51
50
49
48
47
46
45
44
D14
D13
D12
VSS
D11
D10
D9
D8
VCC
D7
D6
D5
D4
VSS
D3
D2
D1
Pin Functions
Address Inputs
Data Input/Output
Chip Select
Write Enable
Output Enable
No Connect
Power (+5V)
Ground
A0 - A16
D0 - D31
CS1~4
WE
OE
NC
V
CC
GND
Package Details
Plastic 68 J-Leaded JEDEC PLCC
D31
A6
A5
A4
A3
A2
A1
A0
VCC
A13
A12
A11
A10
A9
A8
A7
D0
ISSUE 1.5 : December 1998
PUMA 68S4000X - 12/15/20/25
DC OPERATING CONDITIONS
Absolute Maximum Ratings
(1)
Voltage on any pin relative to GND
Power Dissipation
Storage Temperature
DC Output Current
V
T
-0.3 to +7.0
V
4.0
W
P
T
°
T
STG
-55 to +125
C
I
OUT
80
mA
Notes (1) Stresses above those listed may cause permanent damage. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
Recommended Operating Conditions
Parameter
Supply Voltage
Max Terminal Voltage
Input High Voltage
Input Low Voltage
Operating Temperature
Symbol
V
CC
V
TERM
V
IH
V
IL (1)
T
A
T
AI
min
4.5
-0.3
2.2
-0.3
0
-40
typ
5.0
-
-
-
-
-
max
5.5
7.0
Vcc+0.3
0.8
70
85
Units
V
V
V
V
°
C
°
C ( Suffix
I
)
Notes: (1) Pulse width: -3.0V for less than 5ns.
DC Electrical Characteristics
(V
CC
=5V±10%,T
A
=-40°C to +85°C)
Parameter
Input Leakage Current
Output Leakage Current
Symbol Test Condition
I
LI1
I
LO
V
IN
=0V to V
CC
V
I/O
=0V to V
CC
CS
(1)
=V
IL
, I
I/O
=0mA, f=f
max
As above.
As above.
CS
(1)
=V
IH
, f=f
max
, V
IN
=V
IL
or V
IH
CS≥V
CC
-0.2V, 0.2V≥V
IN
≥V
CC
-0.2V,f=0
min
-20
-40
-
-
-
-
-
-
2.4
typ
-
-
-
-
-
-
-
-
-
max
20
40
840
540
400
260
8
0.4
-
Unit
µA
µA
mA
mA
mA
mA
mA
V
V
Operating Supply Current
(2)
32 bit I
CC32
16 bit I
CC16
8 bit I
CC8
Standby Supply Current
(TTL) I
SB
-L Version (CMOS) I
SB1
Output Voltage Low
Output Voltage High
V
OL
V
OH
I
OL
= 8.0mA,V
CC
=Min
I
OH
= -4.0mA,V
CC
=Min
Notes: (1) CS1~4 inputs operate simultaneously for 32 bit mode, in pairs for 16 bit mode and singly for 8 bit
mode.
(2) At f=f
max
address and data inputs are cycling at max frequency.
Capacitance
(V
CC
=5V, T
A
=25°C, F=1Mhz)
Parameter
Input Capacitance
Address,OE,WE
Output Capacitance
8-bit mode (worst case)
Symbol
C
IN1
C
I/O
Test Condition
V
IN
=0V
V
I/O
=0V
min
-
-
typ
-
-
max
34
42
Unit
pF
pF
Note: These parameters are calculated, not measured.
2
PUMA 68S4000X - 12/15/20/25
ISSUE 1.5 : December 1998
AC Test Conditions
*Input pulse levels: 0.0V to 3.0V
*Input rise and fall times: 3 ns
*Input and Output timing reference levels: 1.5V
*V
cc
=5V±10%
*PUMA module is tested in 32 bit mode.
Output Load
I/O Pin
166
Ω
1.76V
30pF
Operation Truth Table
CS1 CS2 CS3 CS4
L
H
H
H
L
H
L
L
H
H
H
L
H
L
X
H
H
L
H
H
L
H
L
H
L
H
H
L
H
L
X
H
H
H
L
H
H
L
L
H
H
L
H
H
L
L
X
H
H
H
H
L
H
L
L
H
H
H
L
H
L
L
X
H
OE
X
X
X
X
X
X
X
L
L
L
L
L
L
L
H
X
WE
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
X
SUPPLY CURRENT
I
CC8
I
CC8
I
CC8
I
CC8
I
CC16
I
CC16
I
CC32
I
CC8
I
CC8
I
CC8
I
CC8
I
CC16
I
CC16
I
CC32
I
CC32
/I
CC16
/I
CC8
I
SB
,I
SB1
MODE
Write D
0~7
Write D
8~15
Write D
16~23
Write D
24~31
Write D
0~15
Write D
16~31
Write D
0~31
Read D
0~7
Read D
8~15
Read D
16~23
Read D
24~31
Read D
0~15
Read D
16~31
Read D
0~31
D
0~31
High-Z
D
0~31
Standby
Notes : H = V
IH
: L =V
IL
: X = V
IH
or V
IL
Low Vcc Data Retention Characteristics - L version only
Parameter
V
CC
for Data Retention
Data Retention Current
Data Retention Time
Operation Recovery Time
Symbol
V
DR
I
CCDR1(1)
t
CDR
t
R
Test Condition
CS=V
CC
-0.2V
V
CC
= 2.0V, CS > V
CC
-0.2V, V
IN
>0V
See Retention Waveform
See Retention Waveform
min
2.0
-
typ
-
-
-
-
max
-
2.2
-
-
Unit
V
mA
ns
ns
0
t
RC
3
ISSUE 1.5 : December 1998
PUMA 68S4000X - 12/15/20/25
AC OPERATING CONDITIONS
Read Cycle
Parameter
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Enable to Output Valid
Output Hold from Address Change
Chip Selection to Output in Low Z
Output Enable to Output in Low Z
Chip Deselection to Output in High Z
Output Disable to Output in High Z
Symbol
t
RC
t
AA
t
ACS
t
OE
t
OH
t
CLZ
t
OLZ
t
CHZ
t
OHZ
12
min max
12
-
-
-
3
2
0
0
0
-
12
12
7
-
-
-
6
5
15
min max
15
-
-
-
3
2
0
0
0
-
15
15
8
-
-
-
8
7
20
min max
20
-
-
-
3
3
0
0
0
-
20
20
10
-
-
-
9
8
25
min max
25
-
-
-
3
3
0
0
0
-
25
25
13
-
-
-
10
10
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Cycle
Parameter
Write Cycle Time
Chip Selection to End of Write
Address Valid to End of Write
Address Setup Time
Write Pulse Width
Write Recovery Time
Data to Write Time Overlap
Output Active from End of Write
Data Hold from Write Time
Write to Output High Z
Symbol
t
WC
t
CW
t
AW
t
AS
t
WP
t
WR
t
DW
t
OW
t
DH
t
WHZ
12
min max
12
10
10
0
10
0
7
0
0
6
-
-
-
-
-
-
-
-
-
-
15
min max
15
12
12
0
12
0
9
0
0
-
-
-
-
-
-
-
-
-
-
7
20
min max
20
15
15
0
15
0
12
0
0
-
-
-
-
-
-
-
-
-
-
10
25
min max Units
25
20
20
0
20
0
15
0
0
-
-
-
-
-
-
-
-
-
-
12
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
PUMA 68S4000X - 12/15/20/25
ISSUE 1.5 : December 1998
Read Cycle Timing Waveform
(1,2)
t
RC
Address
t
AA
OE
t
OE
t
OLZ
t
OH
CS1~4
t
ACS
t
CLZ (4,5)
t
OHZ (3)
Don't
care.
Dout
Data Valid
t
CHZ (3,4,5)
AC Read Characteristics Notes
(1) WE is High for Read Cycle.
(2) All read cycle timing is referenced from the last valid address to the first transition address.
(3) t
CHZ
and t
OHZ
are defined as the time at which the outputs achieve open circuit conditions and are not
referenced to output voltage levels.
(4) At any given temperature and voltage condition, t
CHZ
(max) is less than t
CLZ
(min) both for a given module
and from module to module.
(5) These parameters are sampled and not 100% tested.
Write Cycle No.1 Timing Waveform
(1,4)
t
WC
Address
t
WR(7)
OE
t
AS(6)
t
AW
t
CW
CS1~4
Don't
Care
WE
t
OHZ(3,9)
t
WP(2)
High-Z
t
DW
t
OW
(8)
Dout
High-Z
t
DH
Din
Data Valid
5
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