LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-
2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
ICS853011C
Features
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Two differential 2.5V or 3.3V LVPECL/ECL outputs
One differential PCLK, nPCLK input pair
PCLK, nPCLK pair can accept the following differential input
levels: LVPECL, LVDS, CML, SSTL
Output frequency: >2.5GHz
Translates any single ended input signal to 3.3V
LVPECL levels with resistor bias on nPCLK input
Additive phase jitter, RMS: 0.16ps (typical)
Output skew: 15ps (maximum)
Part-to-part skew: 130ps (maximum)
Propagation delay: 330ps (maximum)
LVPECL mode operating voltage supply range:
V
CC
= 2.375V to 3.8V, V
EE
= 0V
ECL mode operating voltage supply range:
V
CC
= 0V, V
EE
= -3.8V to -2.375V
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
General Description
The ICS853011C is a low skew, high performance
1-to-2 Differential-to-2.5V, 3.3V LVPECL/ECL
HiPerClockS™
Fanout Buffer and a member of the HiPerClockS ™
family of High Performance Clock Solutions from
IDT. The ICS853011C is characterized to operate
from either a 2.5V or a 3.3V power supply. Guaranteed output and
part-to-part skew characteristics make the ICS853011C ideal for
those clock distribution applications demanding well defined
performance and repeatability.
ICS
Block Diagram
Q0
PCLK
Pulldown
nPCLK
Pullup/Pulldown
nQ0
Pin Assignment
Q0
nQ0
Q1
nQ1
1
2
3
4
8
7
6
5
V
CC
PCLK
nPCLK
V
EE
Q1
nQ1
ICS853011C
8 Lead SOIC, 150MIL
3.90mm x 4.90mm x 1.37mm
package body
M Package
Top View
ICS853011C
8 Lead TSSOP, 118mil
3.0mm x 3.0mm x 0.97
package body
G Package
Top View
IDT™ / ICS™
2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
1
ICS853011CM REV. A JULY 28, 2008
ICS853011C
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL FANOUT BUFFER
Table 1. Pin Descriptions
Number
1, 2
3, 4
5
6
7
8
Name
Q0, nQ0
Q1, nQ1
V
EE
nPCLK
PCLK
V
CC
Output
Output
Power
Input
Input
Power
Pullup/
Pulldown
Pulldown
Type
Description
Differential output pair. LVPECL/ECL interface levels.
Differential output pair. LVPECL/ECL interface levels.
Negative supply pin.
Inverting differential LVPECL clock input. V
CC
/2 default when left floating.
Non-inverting differential LVPECL clock input.
Positive supply pin.
NOTE:
Pullup and Pulldown
refers to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
R
PULLUP
R
PULLDOWN
Parameter
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
37
75
Maximum
Units
k
Ω
k
Ω
IDT™ / ICS™
2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
2
ICS853011CM REV. A JULY 28, 2008
ICS853011C
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL FANOUT BUFFER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Negative Supply Voltage, V
EE
Inputs, V
I
(LVPECL mode)
Inputs, V
I
(ECL mode)
Outputs, I
O
Continuos Current
Surge Current
Operating Temperature Range, T
A
Storage Temperature, T
STG
Package Thermal Impedance,
θ
JA
(Junction-to-Ambient) for 8 Lead SOIC
Package Thermal Impedance,
θ
JA
(Junction-to-Ambient) for 8 Lead TSSOP
Rating
4.6V (LVPECL mode, V
EE
= 0V)
-4.6V (ECL mode, V
CC
= 0V)
-0.5V to V
CC
+ 0.5V
0.5V to V
EE
– 0.5V
50mA
100mA
-40°C to 85°C
-65°C to 150°C
112.7°C/W (0 lfpm)
101.7°C/W (0 mps)
DC Electrical Characteristics
Table 3A. Power Supply DC Characteristics,
V
CC
= 2.375V to 3.8V; V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
CC
I
EE
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.375
Typical
3.3
Maximum
3.8
24
Units
V
mA
IDT™ / ICS™
2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
3
ICS853011CM REV. A JULY 28, 2008
ICS853011C
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL FANOUT BUFFER
Table 3B. LVPECL DC Characteristics,
V
CC
= 3.3V; V
EE
= 0V, T
A
= -40°C to 85°C
-40°C
Symbol
V
OH
V
OL
V
PP
V
CMR
I
IH
I
IL
Parameter
Output High Current; NOTE 1
Output Low Current; NOTE 1
Peak-to-Peak Input Voltage
Input High Voltage Common
Mode Range; NOTE 2, 3
Input
High Current
Input
Low Current
PCLK/nPCLK
PCLK
nPCLK
-10
-150
Min
2.175
1.405
150
1.2
Typ
2.275
1.545
800
Max
2.38
1.68
1200
3.3
150
-10
-150
Min
2.225
1.425
150
1.2
25°C
Typ
2.295
1.52
800
Max
2.37
1.615
1200
3.3
150
-10
-150
Min
2.22
1.44
150
1.2
80°C
Typ
2.295
1.535
800
Max
2.365
1.63
1200
3.3
150
Units
V
V
V
V
µA
µA
µA
Input and output parameters vary 1:1 with V
CC
. V
EE
can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50
Ω
to V
CC
– 2V.
NOTE 2: Common mode voltage is defined as V
IH
.
NOTE 3: For single-ended applications, the maximum input voltage for PCLK, nPCLK is V
CC
+ 0.3V.
Table 3C. LVPECL DC Characteristics,
V
CC
= 2.5V; V
EE
= 0V, T
A
= -40°C to 85°C
-40°C
Symbol
V
OH
V
OL
V
PP
V
CMR
I
IH
I
IL
Parameter
Output High Current; NOTE 1
Output Low Current; NOTE 1
Peak-toPeak Input Voltage
Input High Voltage Common
Mode Range; NOTE 2, 3
Input
High Current
Input
Low Current
PCLK/nPCLK
PCLK
nPCLK
-10
-150
Min
1.375
0.605
150
1.2
Typ
1.475
0.745
800
Max
1.58
0.88
1200
2.5
150
-10
-150
Min
1.425
0.625
150
1.2
25°C
Typ
1.495
0.72
800
Max
1.57
0.815
1200
2.5
150
-10
-150
Min
1.42
0.64
150
1.2
80°C
Typ
1.495
0.735
800
Max
1.565
0.83
1200
2.5
150
Units
V
V
V
V
µA
µA
µA
Input and output parameters vary 1:1 with V
CC
. V
EE
can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50
Ω
to V
CC
– 2V.
NOTE 2: Common mode voltage is defined as V
IH
.
NOTE 3: For single-ended applications, the maximum input voltage for PCLK, nPCLK is V
CC
+ 0.3V.
IDT™ / ICS™
2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
4
ICS853011CM REV. A JULY 28, 2008
ICS853011C
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL FANOUT BUFFER
Table 3D. ECL DC Characteristics,
V
CC
= 0V; V
EE
= -3.8V to -2.375V, T
A
= -40°C to 85°C
-40°C
Symbol Parameter
V
OH
V
OL
V
PP
V
CMR
I
IH
I
IL
Output High Current; NOTE 1
Output Low Current; NOTE 1
Peak-toPeak Input Voltage
Input High Voltage Common
Mode Range; NOTE 2, 3
Input
High Current
Input
Low Current
PCLK/
nPCLK
PCLK
nPCLK
-10
-150
Min
-1.125
-1.895
150
V
EE
+1.2
Typ
-1.025
-1.755
800
Max
-0.92
-1.62
1200
0
150
-10
-150
Min
-1.075
-1.875
150
V
EE
+1.2
25°C
Typ
-1.005
-1.78
800
Max
-0.93
-1.685
1200
0
150
-10
-150
Min
-1.08
-1.86
150
V
EE
+1.2
80°C
Typ
-1.005
-1.765
800
Max
-0.935
-1.67
1200
0
150
Units
V
V
V
V
µA
µA
µA
Input and output parameters vary 1:1 with V
CC
. V
EE
can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50
Ω
to V
CC
– 2V.
NOTE 2: Common mode voltage is defined as V
IH
.
NOTE 3: For single-ended applications, the maximum input voltage for PCLK, nPCLK is V
CC
+ 0.3V.
AC Electrical Characteristics
Table 4. AC Characteristics,
V
CC
= 0V; V
EE
= -3.8V to -2.375V or, V
CC
= 2.375V to 3.8V; V
EE
= 0V, T
A
= -40°C to 85°C
-40°C
Symbol
f
MAX
t
PD
tjit
tsk(o)
tsk(pp)
t
R
/ t
F
odc
Parameter
Output Frequency
Propagation Delay; NOTE 1
Additive Phase Jitter, RMS; refer
to Additive Phase Jitter section
Output Skew; NOTE 2, 4
Part-to-Part Skew; NOTE 3, 4
Output
Rise/Fall Time
20% to 80%
100
48
170
0.16
15
150
250
52
100
48
Min
Typ
Max
>2.5
320
180
0.16
15
150
250
52
100
48
Min
25°C
Typ
Max
>2.5
330
190
0.16
15
150
250
52
Min
80°C
Typ
Max
>2.5
345
Units
GHz
ps
ps
ps
ps
ps
%
Output Duty Cycle
All parameters are measured at f
≤
1.4GHz, unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions.
Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
IDT™ / ICS™
2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
5
ICS853011CM REV. A JULY 28, 2008
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