– Compatible with Hot-Plug I/O expanders used on PC mother-
boards
Power Management
– Utilizes advanced low-power design techniques to achieve low
typical power consumption
– Supports PCI Power Management Interface specification (PCI-
PM 1.2)
– Unused SerDes are disabled.
– Supports Advanced Configuration and Power Interface Speci-
fication, Revision 2.0 (ACPI) supporting active link state
Testability and Debug Features
– Built in Pseudo-Random Bit Stream (PRBS) generator
– Numerous SerDes test modes
– Ability to bypass link training and force any link into any mode
– Provides statistics and performance counters
Block Diagram
4-Port Switch Core / 4 PCI Express Lanes
Frame Buffer
Route Table
Port
Arbitration
Scheduler
Transaction Layer
Data Link Layer
Transaction Layer
Data Link Layer
Transaction Layer
Data Link Layer
Transaction Layer
Data Link Layer
Mux / Demux
Phy
Logical
Layer
Mux / Demux
Phy
Logical
Layer
Mux / Demux
Phy
Logical
Layer
Mux / Demux
Phy
Logical
Layer
SerDes
SerDes
SerDes
SerDes
(Port 0)
(Port 2)
(Port 3)
(Port 4)
Figure 1 Internal Block Diagram
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
1 of 30
June 12, 2014
IDT 89HPES4T4 Data Sheet
5 General Purpose Input/Output Pins
– Each pin may be individually configured as an input or output
– Each pin may be individually configured as an interrupt input
– Each pin has a selectable alternate function
Option A Package: 13mm x 13mm 144-ball BGA with 1mm ball spacing
Option B Package: 10mm x 10mm 132-ball QFN with 1mm ball spacing
Product Description
Utilizing standard PCI Express interconnect, the PES4T4 provides the most efficient fan-out solution for applications requiring x1 connectivity, low
latency, and simple board layout with a minimum number of board layers. Each lane provides 2.5 Gbps of bandwidth in both directions and is fully
compliant with PCI Express Base specification 1.1.
The PES4T4 is based on a flexible and efficient layered architecture. The PCI Express layer consists of SerDes, Physical, Data Link and Transac-
tion layers in compliance with PCI Express Base specification Revision 1.1. The PES4T4 can operate either as a store and forward or cut-through
switch and is designed to switch memory and I/O transactions. It supports eight Traffic Classes (TCs) and one Virtual Channel (VC) with sophisticated
resource management to allow efficient switching for applications requiring additional narrow port connectivity and also some high-end connectivity.
Processor
Processor
North
Bridge
Memory
Memory
Memory
Memory
South
Bridge
x1
PES4T4
x1
GE
LOM
x1
GE
LOM
x1
1394
Figure 2 I/O Expansion Application
SMBus Interface
The PES4T4 contains an SMBus master interface. This master interface allows the default configuration register values of the PES4T4 to be over-
ridden following a reset with values programmed in an external serial EEPROM. The master interface is also used by an external Hot-Plug I/O
expander. Two pins make up the SMBus master interface. These pins consist of an SMBus clock pin and an SMBus data pin.
Hot-Plug Interface
The PES4T4 supports PCI Express Hot-Plug on each downstream port. To reduce the number of pins required on the device, the PES4T4 utilizes
an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. Following reset and configuration, when-
ever the state of a Hot-Plug output needs to be modified, the PES4T4 generates an SMBus transaction to the I/O expander with the new value of all of
the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is received on the IOEXPINTN input pin (alternate
function of GPIO) of the PES4T4. In response to an I/O expander interrupt, the PES4T4 generates an SMBus transaction to read the state of all of the
Hot-Plug inputs from the I/O expander.
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June 12, 2014
IDT 89HPES4T4 Data Sheet
General Purpose Input/Output
The PES4T4 provides 5 General Purpose Input/Output (GPIO) pins that may be used by the system designer as bit I/O ports. Each GPIO pin may
be configured independently as an input or output through software control, and some GPIO pins are shared with another on-chip functions. These
alternate functions may be enabled via software or serial configuration EEPROM.
Pin Description
The following tables lists the functions of the pins provided on the PES4T4. Some of the functions listed may be multiplexed onto the same pin. The
active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low) level.
All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.
Signal
PE0RP[0]
PE0RN[0]
PE0TP[0]
PE0TN[0]
PE2RP[0]
PE2RN[0]
PE2TP[0]
PE2TN[0]
PE3RP[0]
PE3RN[0]
PE3TP[0]
PE3TN[0]
PE4RP[0]
PE4RN[0]
PE4TP[0]
PE4TN[0]
PEREFCLKP
PEREFCLKN
Type
I
O
I
O
I
O
I
O
I
Name/Description
PCI Express Port 0 Serial Data Receive.
Differential PCI Express receive
pair for port 0.
PCI Express Port 0 Serial Data Transmit.
Differential PCI Express trans-
mit pair for port 0.
PCI Express Port 2 Serial Data Receive.
Differential PCI Express receive
pair for port 2.
PCI Express Port 2 Serial Data Transmit.
Differential PCI Express trans-
mit pair for port 2.
PCI Express Port 3 Serial Data Receive.
Differential PCI Express receive
pair for port 3.
PCI Express Port 3 Serial Data Transmit.
Differential PCI Express trans-
mit pair for port 3.
PCI Express Port 4 Serial Data Receive.
Differential PCI Express receive
pair for port 4.
PCI Express Port 4 Serial Data Transmit.
Differential PCI Express trans-
mit pair for port 4.
PCI Express Reference Clock.
Differential reference clock pair input. This
clock is used as the reference clock by on-chip PLLs to generate the clocks
required for the system logic and on-chip SerDes.
Table 1 PCI Express Interface Pins
Signal
MSMBCLK
MSMBDAT
Type
I/O
I/O
Name/Description
Master SMBus Clock.
This bidirectional signal is used to synchronize
transfers on the master SMBus.
Master SMBus Data.
This bidirectional signal is used for data on the mas-
ter SMBus.
Table 2 SMBus Interface Pins
3 of 30
June 12, 2014
IDT 89HPES4T4 Data Sheet
Signal
GPIO[0]
Type
I/O
Name/Description
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P2RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 2
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P4RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 4
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
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