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5962F9863201V9A: 产品描述AC SERIES, DUAL POSITIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, UUC16, DIE-16; 产品类别逻辑逻辑; 文件大小38KB，共2页; 制造商Renesas(瑞萨电子); 官网地址https://www.renesas.com/

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5962F9863201V9A概述

AC SERIES, DUAL POSITIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, UUC16, DIE-16

5962F9863201V9A规格参数

参数名称	属性值
零件包装代码	DIE
包装说明	DIE,
针数	16
Reach Compliance Code	unknown
系列	AC
JESD-30 代码	S-XUUC-N16
JESD-609代码	e0
逻辑集成电路类型	J-K FLIP-FLOP
位数	2
功能数量	2
端子数量	16
最高工作温度	125 °C
最低工作温度	-55 °C
输出极性	COMPLEMENTARY
封装主体材料	UNSPECIFIED
封装代码	DIE
封装形状	SQUARE
封装形式	UNCASED CHIP
传播延迟（tpd）	25 ns
认证状态	Not Qualified
筛选级别	MIL-PRF-38535 Class V
最大供电电压 (Vsup)	5.5 V
最小供电电压 (Vsup)	4.5 V
标称供电电压 (Vsup)	5 V
表面贴装	YES
技术	CMOS
温度等级	MILITARY
端子面层	TIN LEAD
端子形式	NO LEAD
端子位置	UPPER
总剂量	300k Rad(Si) V
触发器类型	POSITIVE EDGE
最小 fmax	62 MHz
Base Number Matches	1

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ACS109MS

Data Sheet

July 1999

File Number

4760

Radiation Hardened Dual J-K Flip-Flop

with Set and Reset

The Radiation Hardened ACS109MS is a Dual J-K Flip-

Flop with Set and Reset. These Flip-Flops have

independent J, K, Set, Reset, and Clock inputs and Q and

Q outputs. The outputs change state on the positive-going

transition of the clock. Set and Reset are accomplished

asynchronously by Low-level inputs. All inputs are buffered

and the outputs are designed for balanced propagation

delay and transition times.

The ACS109MS is fabricated on a CMOS Silicon on

Sapphire (SOS) process, which provides an immunity to

Single Event Latch-up and the capability of highly reliable

performance in any radiation environment. These devices

offer significant power reduction and faster performance

when compared to ALSTTL types.

Speciﬁcations for Rad Hard QML devices are controlled

by the Defense Supply Center in Columbus (DSCC). The

SMD numbers listed below must be used when ordering.

Detailed Electrical Speciﬁcations for the ACS109MS are

contained in SMD 5962-98632. A “hot-link” is provided

on our homepage for downloading.

http://www.intersil.com/spacedefense/spaceselect.htm

Features

• QML Qualiﬁed Per MIL-PRF-38535 Requirements

• 1.25 Micron Radiation Hardened SOS CMOS

• Radiation Environment

- Latch-Up Free Under Any Conditions

- Total Dose (Max.) . . . . . . . . . . . . . . . . . 3 x 10

RAD(Si)

- SEU Immunity . . . . . . . . . . . . . <1 x 10

-10

Errors/Bit/Day

- SEU LET Threshold . . . . . . . . . . . . >100MeV/(mg/cm

)

• Input Logic Levels. . . . V

= (0.3)(V

), V

= (0.7)(V

)

• Output Current

. . . . . . . . . . . . . . . . . . . . . . . . . . ±12mA

(Min)

• Quiescent Supply Current . . . . . . . . . . . . . . . 10µA (Max)

• Propagation Delay . . . . . . . . . . . . . . . . . . . . . . 25ns (Max)

Applications

• High Speed Control Circuits

• Sensor Monitoring

• Low Power Designs

Ordering Information

ORDERING NUMBER

5962F9863201VCC

ACS109D/SAMPLE-03

5962F9863201VXC

ACS109K/SAMPLE-03

5962F9863201V9A

INTERNAL MARKETING

NUMBER

ACS109DMSR-03

ACS109D/SAMPLE-03

ACS109KMSR-03

ACS109K/SAMPLE-03

ACS109HMSR-03

TEMP. RANGE (

-55 to 125

PACKAGE

16 Ld SBDIP

16 Ld Flatpack

Die

DESIGNATOR

CDIP2-T16

CDFP4-F16

Pinouts

ACS109MS

(SBDIP)

TOP VIEW

1R 1

1J 2

1K 3

1CP 4

1S 5

1Q 6

1Q 7

GND 8

16 V

15 2R

14 2J

13 2K

12 2CP

11 2S

10 2Q

9 2Q

1CP

GND

ACS109MS

(FLATPACK)

TOP VIEW

2CP

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

5962F9863201V9A相似产品对比

	5962F9863201V9A	5962F9863201VXC	5962F9863201VCC
描述	AC SERIES, DUAL POSITIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, UUC16, DIE-16	AC SERIES, DUAL POSITIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDFP16, CERAMIC, DFP-16	AC SERIES, DUAL POSITIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP16, SIDE BRAZED, CERAMIC, DIP-16
零件包装代码	DIE	DFP	DIP
包装说明	DIE,	DFP, FL16,.3	SIDE BRAZED, CERAMIC, DIP-16
针数	16	16	16
Reach Compliance Code	unknown	_compli	unknown
系列	AC	AC	AC
JESD-30 代码	S-XUUC-N16	R-CDFP-F16	R-CDIP-T16
JESD-609代码	e0	e0	e4
逻辑集成电路类型	J-K FLIP-FLOP	J-K FLIP-FLOP	J-K FLIP-FLOP
位数	2	2	2
功能数量	2	2	2
端子数量	16	16	16
最高工作温度	125 °C	125 °C	125 °C
最低工作温度	-55 °C	-55 °C	-55 °C
输出极性	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY
封装主体材料	UNSPECIFIED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED
封装代码	DIE	DFP	DIP
封装形状	SQUARE	RECTANGULAR	RECTANGULAR
封装形式	UNCASED CHIP	FLATPACK	IN-LINE
传播延迟（tpd）	25 ns	25 ns	25 ns
认证状态	Not Qualified	Not Qualified	Not Qualified
筛选级别	MIL-PRF-38535 Class V	MIL-PRF-38535 Class V	MIL-PRF-38535 Class V
表面贴装	YES	YES	NO
技术	CMOS	CMOS	CMOS
温度等级	MILITARY	MILITARY	MILITARY
端子面层	TIN LEAD	Tin/Lead (Sn/Pb)	GOLD
端子形式	NO LEAD	FLAT	THROUGH-HOLE
端子位置	UPPER	DUAL	DUAL
总剂量	300k Rad(Si) V	300k Rad(Si) V	300k Rad(Si) V
触发器类型	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE
Base Number Matches	1	1	1
最大供电电压 (Vsup)	5.5 V	5.5 V	-
最小供电电压 (Vsup)	4.5 V	4.5 V	-
标称供电电压 (Vsup)	5 V	5 V	-
最小 fmax	62 MHz	62 MHz	-
座面最大高度	-	2.92 mm	5.08 mm
端子节距	-	1.27 mm	2.54 mm
宽度	-	6.73 mm	7.62 mm

5962F9863201V9A

5962F9863201V9A概述

5962F9863201V9A规格参数

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