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MT58V512V36PT-7.5IT

产品描述SRAM
产品类别存储    存储   
文件大小535KB,共34页
制造商Micron Technology
官网地址http://www.mdtic.com.tw/
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MT58V512V36PT-7.5IT概述

SRAM

MT58V512V36PT-7.5IT规格参数

参数名称属性值
包装说明,
Reach Compliance Codeunknown
Base Number Matches1

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18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, SCD SYNCBURST SRAM
18Mb
SRAM
Features
SYNCBURST
MT58L1MY18P, MT58V1MV18P,
MT58L512Y32P, MT58V512V32P,
MT58L512Y36P, MT58V512V36P
3.3V V
DD
, 3.3V or 2.5V I/O; 2.5V V
DD
, 2.5V I/O
• Fast clock and OE# access times
• Single 3.3V ±5 percent or 2.5V ±5 percent power
supply
• Separate 3.3V ±5 percent or 2.5V ±5 percent isolated
output buffer supply (V
DD
Q)
• SNOOZE MODE for reduced-power standby
• Single-cycle deselect (Pentium
®
BSRAM-
compatible)
• Common data inputs and data outputs
• Individual byte write control and global write
• Three chip enables for simple depth expansion and
address pipelining
• Clock-controlled and registered addresses, data
I/Os, and control signals
• Internally self-timed WRITE cycle
• Burst control (interleaved or linear burst)
• Low capacitive bus loading
Figure 1: 100-Pin TQFP
JEDEC-Standard MS-026 BHA (LQFP)
Figure 2: 165-Ball FBGA
JEDEC-Standard MS-216 (Var. CAB-1)
Options
• Timing (Access/Cycle/MHz)
3.1ns/5ns/200 MHz
3.5ns/6ns/166 MHz
4.2ns/7.5ns/133 MHz
5ns/10ns/100 MHz
• Configurations
3.3V V
DD
, 3.3V or 2.5V I/O
1 Meg x 18
512K x 32
512K x 36
2.5V V
DD
, 2.5V I/O
1 Meg x 18
512K x 32
512K x 36
• Packages
100-pin TQFP
165-ball, 13mm x 15mm FBGA
• Operating Temperature Range
Commercial (0ºC
£
T
A
£
+70ºC)
Industrial (-40ºC
£
T
A
£
+85ºC)
NOTE:
TQFP
Marking
-5
-6
-7.5
-10
MT58L1MY18P
MT58L512Y32P
MT58L512Y36P
MT58V1MV18P
MT58V512V32P
MT58V512V36P
T
F
1
None
IT
2
Part Number Example:
MT58L512Y36PT-10
General Description
The Micron
®
SyncBurst™ SRAM family employs
high-speed, low-power CMOS designs that are fabri-
cated using an advanced CMOS process.
Micron’s 18Mb SyncBurst SRAMs integrate a 1 Meg x
18, 512K x 32, or 512K x 36 SRAM core with advanced
synchronous peripheral circuitry and a 2-bit burst
counter. All synchronous inputs pass through registers
controlled by a positive-edge-triggered single-clock
input (CLK). The synchronous inputs include all
addresses, all data inputs, active LOW chip enable
(CE#), two additional chip enables for easy depth
expansion (CE2, CE2#), burst control inputs (ADSC#,
1
©2003 Micron Technology, Inc.
1. A Part Marking Guide for the FBGA devices can be found on
Micron’s Web site—http://www.micron.com/numberguide.
2. Contact factory for availability of Industrial Temperature
devices.
18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM
MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.

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