Datasheet
V850ES/FE3-L
32-bit Single-Chip Microcontroller
Hardware
µPD70F3610(A)
µPD70F3610(A1)
µPD70F3610(A2)
µPD70F3613(A)
µPD70F3613(A1)
µPD70F3613(A2)
µPD70F3611(A)
µPD70F3611(A1)
µPD70F3611(A2)
µPD70F3614(A)
µPD70F3614(A1)
µPD70F3614(A2)
µPD70F3612(A)
µPD70F3612(A1)
µPD70F3612(A2)
Document No. U19190EE1V0DS00
Date Published March 2008
©
NEC Electronics 2008
Printed in Germany
V850ES/FE3-L
Notes for CMOS Devices
1.
Precaution against ESD for semiconductors
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2.
Handling of unused input pins for CMOS
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to
the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3.
Status before initialization of MOS devices
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not
guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset
signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
2
Datasheet U19190EE1V0DS00
V850ES/FE3-L
Legal Notes
• The information in this document is current as of January 2007. The information is subject to change
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"NEC Electronics products" means any product developed or manufactured by or for NEC
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SuperFlash® is a registered trademark of Silicon Storage Technology, Inc. in several coun-
tries including the United States and Japan. This product uses SuperFlash® technology
licensed from Silicon Storage Technology, Inc.
Datasheet U19190EE1V0DS00
3
V850ES/FE3-L
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
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Device availability
Ordering information
Product release schedule
Availability of related technical literature
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
• Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
For further information please contact:
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•
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4
Datasheet U19190EE1V0DS00
V850ES/FE3-L
Table of Contents
1.
1.1
1.2
1.3
1.4
1.5
1.6
1.7
Pin Group Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Device package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Groups 1x: Pins supplied by EVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Groups 2x: Pins supplied by EVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Groups 3x: Pins supplied by BVDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Groups 4: Pins supplied by AVREF0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Groups 6: Pins supplied by EVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Groups 7: Pins supplied by VRO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.
2.1
2.2
2.3
2.4
2.5
2.5.1
2.5.2
2.5.3
2.5.4
2.6
2.6.1
2.6.2
2.6.3
2.6.3.1
2.7
2.7.1
2.7.2
2.7.3
2.7.4
2.7.5
2.7.6
2.7.7
2.7.8
2.8
2.9
2.10
2.11
2.12
2.13
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Capacities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Voltage Regulator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Clock Generator Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Main System Clock Oscillation Circuit Characteristics . . . . . . . . . . . . . . . . . . . . . . 11
Sub System Clock Oscillation Circuit Characteristics . . . . . . . . . . . . . . . . . . . . . . . 12
Internal-OSC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Input/Output Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
PIN leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Power supply current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
FE3-L µPD70F3610, µPD70F3611, µPD70F3612, µPD70F3613, µPD70F3614 . . . . . 16
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
CLKOUT Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
RESET, Interrupt, ADTRG Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Key Return Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Timer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
CSI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
UART Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
IIC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
CAN Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
POC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
LVI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
RAM Retention Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Data Retention Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Flash Memory Programming Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.
3.1
3.2
3.2.1
3.2.2
Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Package Dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Product Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Marking of pin 1 at a QFP (Quad Flat Package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Identification of Lead-Free Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.
Change History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Datasheet U19190EE1V0DS00
5
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