The SM802xxx series is a member of the ClockWorks™
family of devices from Micrel and provide an extremely
low-noise timing solution for applications such as (1-100)
Gigabit Ethernet, SONET, Wireless base station, Satellite
communication, Fibre Channel, SAS/SATA and PCI-e. It is
based upon a unique PLL architecture that provides less
than 250fs phase jitter.
The devices operate from a 2.5V or 3.3V power supply
and synthesize up to 8 different combinations (LVPECL,
LVDS, HCSL) of differential or 16 single ended output
clocks. The devices accept an external reference clock or
crystal input.
The SM802xxx series is fully programmable and a web
tool is available to configure a part for samples at:
http://clockworks.micrel.com/micrel/
Datasheets and support documentation are available on
Micrel’s web site at:
www.micrel.com.
Features
•
115fs at 156.25MHz (1.875MHz to 20MHz)
•
245fs at 156.25MHz (12kHz to 20MHz)
•
On chip power supply regulation for excellent board
level power supply noise immunity
•
Generates up to 8 combinations of differential or 16
single-ended clock outputs.
−
LVPECL, LVDS, HCSL, LVCMOS (SE or Diff)
•
Selectable input:
−
Crystal: 11MHz to 30MHz
−
Reference input: 11MHz to 80MHz
•
No external crystal oscillator capacitors required
•
2.5V or 3.3V operating power supply
•
Available in Industrial Temperature range
•
Available in Green, RoHS, and PFOS compliant QFN
packages:
−
44-pin, 7mm × 7mm
−
32-pin, 5mm × 5mm
−
24-pin, 4mm × 4mm
−
16-pin, 3mm × 3.5mm
Block Diagram
Applications
•
•
•
•
•
•
•
1/10/40/100 Gigabit Ethernet – (GbE)
SONET/SDH
PCI-Express
CPRI/OBSAI – Wireless base station
Fibre Channel
SAS/SATA
DIMM
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 •
http://www.micrel.com
June 6, 2013
Revision 1.0
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
SM802XXX
Ordering Information
Part Number
SM802xxxUMG
SM802xxxUMGTR
Marking
802xxx
802xxx
Shipping
Tray
Tape and Reel
Ambient Temperature Range
–40°C to +85°C
–40°C to +85°C
Package
See
Package Options
See
Package Options
Package Options
Package
(1)
Option
#1
#2
#3
#4
#5
#6
Note:
1. Use the web tool at
http://clockworks.micrel.com/micrel/
to determine the desired configuration.
QFN Package
44-pin, 7mm × 7mm
32-pin, 5mm × 5mm
24-pin, 4mm × 4mm
24-pin, 4mm × 4mm
16-pin, 3mm × 3.5mm
16-pin, 3mm × 3.5mm
# of
Outputs
8 diff.
4 diff.
4 diff.
2 diff.
2 diff.
2 diff.
Crystal
Yes
Yes
Yes
Yes
No
Yes
Reference
Input
Yes
Yes
Yes
Yes
Yes
No
XTAL_SEL
Yes
Yes
Yes
Yes
No
No
FSEL
Yes
Yes
No
Yes
Yes
No
OE1
OE2
Yes
Yes
No
Yes
No
No
PLL
Bypass
Yes
Yes
Yes
Yes
No
No
June 6, 2013
2
Revision 1.0
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
SM802XXX
Pin Configurations
Option #1
44-Pin 7mm x 7mm QFN (QFN-44L)
Option #2
32-Pin 5mm x 5mm QFN
Option #3
24-Pin 4mm x 4mm QFN
Option #4
24-Pin 4mm x 4mm QFN
Option #5
16-Pin 3mm x 3.5mm QFN
Option #6
16-Pin 3mm x 3.5mm QFN
June 6, 2013
3
Revision 1.0
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
SM802XXX
Pin Description
Pin Numbers by Package Option
#1
44-Pin
18
19
17
14
#2
32-Pin
13
14
12
10
#3
24-Pin
10
11
9
#4
24-Pin
9
10
8
6
7
6
#5
16-Pin
#6
16-Pin
6
7
Pin Name
XIN
XOUT
REF_IN
FSEL
Pin
Type
I, O
(SE)
I, (SE)
I, (SE)
Pin
Level
Pin Function
Crystal connections
LVCMOS Reference Clock input
Frequency Select, divides output
LVCMOS frequencies by 2.
0 = FREQ, 1 = FREQ/2, 45kΩ pull-up
XTAL Select, selects between XTAL and
LVCMOS REF_IN
0 = REF_IN, 1 = XTAL, 45kΩ pull-up
Bypasses the PLL and switches the XTAL
or REF_IN frequency to all outputs
0 = PLL mode, 1 = Bypass mode, 45kΩ
pull-down
Clock Outputs from Bank 1
10
6
6
4
-
-
XTAL SEL
I, (SE)
9
5
5
3
-
-
PLL
BYPASS
I, (SE)
LVCMOS
25
26
28
29
32
33
35
36
41
42
1
2
4
5
7
8
31
37
38
16
43
44
Note:
-
-
-
-
-
/QA
QA
/QB
QB
/QC
QC
/QD
QD
/QE
QE
/QF
QF
/QG
QG
/QH
QH
O
Various
Each output can be programmed to its
own logic type: LVPECL, LVDS, HCSL, or
(2)
LVCMOS
21
22
-
25
26
30
31
16
17
-
20
21
23
24
-
-
-
O
Various
-
19
20
22
23
-
14
15
-
14
15
O
Various
O
Various
Clock Outputs from Bank 2
-
-
O
Various
Each output can be programmed to its
own logic type: LVPECL, LVDS, HCSL, or
(2)
LVCMOS
-
3
4
-
-
3
4
-
-
1
2
-
1
2
-
O
Various
-
O
Various
-
-
-
O
Various
23
27
18
17
16
16
VDDO1
PWR
Power Supply for the outputs on Bank 1.
1
32
1
24
16
16
VDDO2
PWR
Power Supply for the outputs on Bank 2.
2. In the case of LVCMOS, an output pair can provide two single-ended LVCMOS outputs.
June 6, 2013
4
Revision 1.0
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
Pin Numbers by Package Option
#1
44-Pin
24
39
3
6
40
11
20
27
30
34
12
13
#2
32-Pin
19
28
2
29
#3
24-Pin
22
#4
24-Pin
21
#5
16-Pin
-
#6
16-Pin
-
Pin Name
SM802XXX
Pin
Type
Pin
Level
Pin Function
VSSO1
PWR
Power Supply Ground for the outputs on
Bank 1.
Power Supply Ground for the outputs on
Bank 2.
2
2
-
-
VSSO2
PWR
7
15
20
24
8
9
7
12
15
19
5
11
16
18
4
8
11
13
4
8
11
13
TEST
Used for production test.
Do not connect anything to these pins.
8
1
5
3
9
10
12
-
5
3
9
10
12
-
VDD
PWR
Core Power Supply.
21
23
17
18
13
14
13
14
15
-
VSS
PWR
Core Power Supply Ground.
-
-
-
EXPOSED
PAD
OE1
-
The exposed pad must be connected to
the VSS ground plane.
Output Enable 1, OUT1−8 disables to
LVCMOS tri-state,
0 = Disabled, 1 = Enabled, 45kΩ pull-up
Output Enable 2, OUT9−16 disables to
LVCMOS tri-state,
0 = Disabled, 1 = Enabled, 45kΩ pull-up
15
11
-
7
-
-
I, (SE)
22
16
-
12
-
-
OE2
I, (SE)
Truth Table
Control Pin
OE1
OE2
XTAL_SEL
FSEL
(4)
Internal Resistor
Pull-Up
Pull-Up
Pull-Up
Pull-Up
Pull-Down
(3)
0 Level (Low)
Outputs QA~QD disabled to Hi Z (Tri-State)
Outputs QE~QH disabled to Hi Z (Tri-State)
External reference clock input is selected
Output = Target Frequency X2 or /2
PLL frequency is connected to outputs
1 Level (High)
Outputs QA~QD enabled
Outputs QE~QH enabled
Crystal is selected
Output = Target Frequency
PLL is bypassed, Crystal or Ref-in is
connected to outputs
PLL_BYPASS
Notes:
3. The internal resistor sets the default logic level on the control pin when the pin is left open. Pull up will set default logic 1 and pull down will set
default logic 0. When the pin is not available on a specific configuration, the level will be the default logic level.
4. The FSEL pin behavior can be programmed between two types:
-
-
At FSEL=0 (low), the output frequency changes to multiply by 2.
At FSEL=0 (low), the output frequency changes to divide by 2.
The FSEL function affects all outputs the same way, all outputs change when the FSEL pin level changes.
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