74ALVCH16373
Low−Voltage 16−Bit
Transparent Latch with Bus
Hold 1.8/2.5/3.3 V
(3−State, Non−Inverting)
The 74ALVCH16373 is an advanced performance, non−inverting
16−bit transparent latch. It is designed for very high−speed, very
low−power operation in 1.8 V, 2.5 V or 3.3 V systems. The
VCXH16373 is byte controlled, with each byte functioning
identically, but independently. Each byte has separate Output Enable
and Latch Enable inputs. These control pins can be tied together for
full 16−bit operation.
The 74ALVCH16373 contains 16 D−type latches with 3−state
3.6 V−tolerant outputs. When the Latch Enable (LEn) inputs are
HIGH, data on the Dn inputs enters the latches. In this condition, the
latches are transparent, (a latch output will change state each time its D
input changes). When LE is LOW, the latch stores the information that
was present on the D inputs a setup time preceding the
HIGH−to−LOW transition of LE. The 3−state outputs are controlled
by the Output Enable (OEn) inputs. When OE is LOW, the outputs are
enabled. When OE is HIGH, the standard outputs are in the high
impedance state, but this does not interfere with new data entering into
the latches. The data inputs include active bushold circuitry,
eliminating the need for external pull−up resistors to hold unused or
floating inputs at a valid logic state.
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MARKING DIAGRAM
48
48
1
74ALVCH16373DT
AWLYYWW
TSSOP−48
DT SUFFIX
CASE 1201
A
Location
WL
YY
WW
1
= Assembly
= Wafer Lot
= Year
= Work Week
PIN NAMES
Pins
OEn
LEn
D0−D15
O0−O15
Function
Output Enable Inputs
Latch Enable Inputs
Inputs
Outputs
•
Designed for Low Voltage Operation: V
CC
= 1.65
−
3.6 V
•
3.6 V Tolerant Inputs and Outputs
•
High Speed Operation: 3.6 ns max for 3.0 to 3.6 V
•
•
•
•
•
•
•
•
4.5 ns max for 2.3 to 2.7 V
6.8 ns max for 1.65 to 1.95 V
Static Drive:
±24
mA Drive at 3.0 V
±12
mA Drive at 2.3 V
±4
mA Drive at 1.65 V
Supports Live Insertion and Withdrawal
Includes Active Bushold to Hold Unused or Floating Inputs at a Valid
Logic State
I
OFF
Specification Guarantees High Impedance When V
CC
= 0 V
†
Near Zero Static Supply Current in All Three Logic States (40
mA)
Substantially Reduces System Power Requirements
Latchup Performance Exceeds
±250
mA @ 125°C
ESD Performance: Human Body Model >2000V; Machine Model >200V
Second Source to Industry Standard 74ALVCH16373
ORDERING INFORMATION
Device
74ALVCH16373DTR
Package
TSSOP
Shipping
2500/Tape & Reel
†To ensure the outputs activate in the 3−state condition, the output enable pins
should be connected to V
CC
through a pull−up resistor. The value of the resistor is
determined by the current sinking capability of the output connected to the OE pin.
©
Semiconductor Components Industries, LLC, 2006
June, 2006
−
Rev. 2
1
Publication Order Number:
74ALVCH16373/D
74ALVCH16373
MAXIMUM RATINGS
(Note 1)
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
I
GND
T
STG
T
L
T
J
q
JA
MSL
F
R
V
ESD
DC Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Sink Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature Range
Lead Temperature, 1 mm from Case for 10 Seconds
Junction Temperature Under Bias
Thermal Resistance (Note 2)
Moisture Sensitivity
Flammability Rating
ESD Withstand Voltage
Oxygen Index: 30 to 35
Human Body Model (Note 3)
Machine Model (Note 4)
Charged Device Model (Note 5)
Above V
CC
and Below GND at 125°C (Note 6)
V
I
< GND
V
O
< GND
Parameter
Value
*0.5
to
)4.6
*0.5
to
)4.6
*0.5
to
)4.6
*50
*50
$50
$100
$100
*65
to
)150
260
)150
90
Level 1
UL 94 V−O @ 0.125 in
u2000
u200
N/A
$250
V
Unit
V
V
V
mA
mA
mA
mA
mA
°C
°C
°C
°C/W
I
LATCH−UP
Latch−Up Performance
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. I
O
absolute maximum rating must be observed.
2. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2−ounce copper trace with no air flow.
3. Tested to EIA/JESD22−A114−A.
4. Tested to EIA/JESD22−A115−A.
5. Tested to JESD22−C101−A.
6. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
I
V
O
T
A
Dt/DV
Supply Voltage
Input Voltage
Output Voltage
Operating Free−Air Temperature
Input Transition Rise or Fall Rate
V
CC
= 2.5 V
$
V
CC
= 3.0 V
$
0.2 V
0.3 V
Parameter
Operating
Data Retention Only
(Note 7)
(Active State)
(3−State)
Min
2.3
1.5
−0.5
0
0
*40
0
0
Max
3.6
3.6
3.6
3.6
3.6
)85
20
10
Unit
V
V
V
°C
ns/V
7. Unused inputs may not be left open. All inputs must be tied to a high−logic voltage level or a low−logic input voltage level.
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3
74ALVCH16373
AC CHARACTERISTICS
(Note 10; t
R
= t
F
= 2.0 ns; C
L
= 30 pF; R
L
= 500
W)
Limits
T
A
=
−40°C
to +85°C
V
CC
= 3.0 V t o 3.6 V
Symbol
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
s
t
h
t
w
Parameter
Propagation Delay
Dn to On
Propagation Delay
LE to On
Output Enable Time to
High and Low Level
Output Disable Time From
High and Low Level
Setup Time, High or Low Dn to LE
Hold Time, High or Low Dn to LE
LE Pulse Width, High
Waveform
1
1
2
2
3
3
3
Min
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.5
1.0
1.5
Max
3.6
3.6
3.9
3.9
4.7
4.7
4.1
4.1
V
CC
= 2.3 V to 2.7 V
Min
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.5
1.0
1.5
Max
4.5
4.5
4.9
4.9
6.0
6.0
5.1
5.1
V
CC
= 1.65 V to 1.95 V
Min
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
2.5
1.0
4.0
Max
6.8
6.8
7.8
7.8
9.2
9.2
6.8
6.8
Unit
ns
ns
ns
ns
ns
ns
ns
t
OSHL
Output−to−Output Skew
0.5
0.5
0.75
ns
t
OSLH
(Note 11)
0.5
0.5
0.75
10. For C
L
= 50 pF, add approximately 300 ps to the AC maximum specification.
11. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (t
OSHL
) or LOW−to−HIGH (t
OSLH
); parameter
guaranteed by design.
CAPACITIVE CHARACTERISTICS
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Condition
Note 12
Note 12
Note 12, 10 MHz
Typical
6
7
20
Unit
pF
pF
pF
C
PD
Power Dissipation Capacitance
12. V
CC
= 1.8, 2.5 or 3.3 V; V
I
= 0V or V
CC
.
V
IH
Dn
Vm
Vm
0V
t
PLH
On
Vm
t
PHL
V
OH
Vm
V
OL
WAVEFORM 1 − PROPAGATION DELAYS
t
R
= t
F
= 2.0 ns, 10% to 90%; f = 1MHz; t
W
= 500 ns
Figure 4. AC Waveforms
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