SAA7142HL
Dual video input processor
Rev. 01 — 16 January 2006
Product data sheet
1. General description
The SAA7142HL is a combination of two stand-alone multi-standard video decoders.
The SAA7142HL is a pure 3.3 V (5 V tolerant inputs and I/Os) Complementary
Metal-Oxide Semiconductor (CMOS) circuit and a highly integrated circuit for video
surveillance applications. Both video decoders are based on the principle of line-locked
clock decoding and are able to decode the color of Phase Alternating Line (PAL),
Sequentiel Couleur avec Memoire (SECAM) and National Television Standards
Committee (NTSC) signals into
“ITU-R BT 601”
compatible color component values.
The SAA7142HL accepts as analog inputs in total four Color Video Blanking Signal
(CVBS) sources from TV or VTR (two selectable CVBS sources for each decoder).
Each of the video decoders (A and B) contains an analog preprocessing circuit including
source selection for two CVBS sources, anti-aliasing filter and Analog-to-Digital Converter
(ADC), an automatic clamp and gain control, a Clock Generation Circuit (CGC), a digital
multi-standard decoder (PAL, NTSC and SECAM), a Brightness Contrast Saturation
(BCS) control circuit, a multi-standard text slicer (see
Figure 1)
and a 27 MHz Vertical
Blanking Interval (VBI) data bypass.
The integrated high-performance multi-standard data slicer supports several VBI data
standards:
•
Teletext [World Standard Teletext (WST), Chinese teletext (CCST)] (625 lines)
•
Teletext [US-WST, North American Broadcast Text System (NABTS) and Japanese
teletext (MOJI)] (525 lines)
•
•
•
•
•
Closed caption [Europe, US (line 21)]
Wide Screen Signalling (WSS)
Video Programming Signal (VPS)
Vertical Interval Time Codes (VITC) EBU/SMPTE
High-speed VBI data bypass for Intercast application.
The circuit is I
2
C-bus controlled via an I
2
C-bus interface. The video decoders share one
I
2
C-bus interface on different I
2
C-bus slave addresses. Each video decoder of the
SAA7142HL uses a register mapping which is compatible to the SAA7113H register
mapping.
Philips Semiconductors
SAA7142HL
Dual video input processor
2. Features
2.1 General
s
Two stand-alone video decoder instances (A and B) with two selectable CVBS video
inputs each and digital video outputs
s
Programming register mapping identical to SAA7113H
s
Small package (LQFP128)
s
Requires only one crystal (24.576 MHz) for all standards shared by all video decoder
instances
s
CMOS 3.3 V device with 5 V tolerant digital inputs and I/O ports
s
Both decoder instances are I
2
C-bus controlled and share one I
2
C-bus interface (full
read-back ability by an external controller, bit rate up to 400 kbit/s).
2.2 Features of video decoder instances A and B
s
Two analog CVBS inputs with internal analog source selectors
s
One analog preprocessing channel in differential CMOS style with built-in analog
anti-aliasing filter
s
Fully programmable static gain or automatic gain control for the selected CVBS
channel
s
Switchable white peak control
s
Line-locked system clock frequencies
s
Digital Phase-Locked Loop (PLL) for horizontal sync processing and clock generation,
horizontal and vertical sync detection
s
Automatic detection of 50 Hz and 60 Hz field frequency and automatic switching
between PAL and NTSC standards
s
Luminance and chrominance signal processing for PAL BGHI, PAL N,
combination PAL N, PAL M, NTSC M, NTSC N, NTSC 4.43, NTSC Japan and SECAM
s
User-programmable luminance peaking or aperture correction
s
Cross-color reduction for NTSC by chrominance comb filtering
s
PAL delay line for correcting PAL phase errors
s
Brightness Contrast Saturation (BCS) and hue control on-chip
s
Multi-standard VBI data slicer decoding World Standard Teletext (WST), North
American Broadcast Text System (NABTS), closed caption, Wide Screen Signalling
(WSS), Video Programming System (VPS), VITC variants (EBU/SMPTE), etc.
s
Standard ITU-R BT 656 Y-C
B
-C
R
4 : 2 : 2 format (8-bit) on Video Parallel Output (VPO)
bus
s
Enhanced ITU-R BT 656 output format on VPO-bus containing:
x
Active video
x
Decoded VBI data
s
Boundary scan test circuit complies with the
“IEEE Std. 1149.b1 - 1994”.
3. Applications
s
Surveillance application.
9397 750 15208
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 16 January 2006
2 of 63
Philips Semiconductors
SAA7142HL
Dual video input processor
4. Quick reference data
Table 1:
Symbol
V
DDD
V
DDA
T
amb
P
A+D
Quick reference data
Parameter
digital supply voltage
analog supply voltage
ambient temperature
analog and digital power dissipation
Conditions
Min
3.0
3.1
0
-
Typ
3.3
3.3
25
1.1
Max
3.6
3.5
70
-
Unit
V
V
°C
W
5. Ordering information
Table 2:
Ordering information
Package
Name
SAA7142HL
LQFP128
Description
plastic low profile quad flat package; 128 leads; body 14
×
20
×
1.4 mm
Version
SOT425-1
Type number
9397 750 15208
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 16 January 2006
3 of 63
Philips Semiconductors
SAA7142HL
Dual video input processor
6. Block diagram
VIDEO DECODER A
ANALOG
PROCESSING
AND
AI11_A
AI1D_A
AI12_A
ANALOG-TO-
DIGITAL
CONVERSION
AD1
CVBS
CONTROL
ANALOG
PROCESSING
CONTROL
I
2
C-BUS
CONTROL
I
2
C-BUS
INTERFACE
SCL_AB
SDA_AB
I
2
C-BUS
INTERFACE
I
2
C-BUS
CONTROL
ANALOG
PROCESSING
CONTROL
CONTROL
CVBS
AI12_B
AI1D_B
AI11_B
AD1
ANALOG-TO-
DIGITAL
CONVERSION
AND
ANALOG
PROCESSING
Y
CVBS
LUMINANCE
CIRCUIT
SYNCHRONIZATION
CIRCUIT
LFCO
POWER-ON
CONTROL
LLC_B
CLOCK
GENERATION
CIRCUIT
CLOCKS
CHROMINANCE
CIRCUIT AND BCS
BYPASS
VBI DATA BYPASS
UPSAMPLING FILTER
Y
UV
MULTISTANDARD TEXT SLICER
OUTPUT
FORMATTER
VPO[7:0]_A
VBI DATA BYPASS
UPSAMPLING FILTER
BYPASS
CHROMINANCE
CIRCUIT AND BCS
UV
Y
AGND_A
CLOCKS
CVBS
Y
LUMINANCE
CIRCUIT
Y
CLOCK
GENERATION
CIRCUIT
LLC_A
SYNCHRONIZATION
CIRCUIT
LFCO
POWER-ON
CONTROL
Y
AGND_B
OUTPUT
FORMATTER
VIDEO DECODER B
VPO[7:0]_B
MULTISTANDARD TEXT SLICER
SAA7142HL
TEST
CONTROL
BLOCK
FOR
BOUNDARY
SCAN TEST
AND
SCAN TEST
TDI
TCK
TMS
TRST_N
TDO
001aad235
Fig 1. Block diagram of SAA7142HL.
9397 750 15208
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 16 January 2006
4 of 63
Philips Semiconductors
SAA7142HL
Dual video input processor
7. Pinning information
7.1 Pinning
128
103
102
1
SAA7142HL
38
39
64
65
001aad236
Fig 2. Pin configuration for LQFP128.
7.2 Pin description
Table 3:
Symbol
V
SSA1(DECA)
V
DDA1(DECA)
AI11_A
AI12_A
AI1D_A
AGND_A
DNC1
V
DDA0(DECA)
V
SSA0(DECA)
V
SSA1(DECA
V
DDA1(DECA)
DNC2
DNC3
DNC4
AGND_A
DNC5
DNC6
V
DDA0(DECA)
9397 750 15208
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Description
analog ground for analog supply of the Analog-to-Digital Converter
(ADC) of video decoder A
analog supply voltage for the ADC (3.3 V) of video decoder A
analog input 11 of video decoder A
analog input 12 of video decoder A
differential analog input for AI11 and AI12 of video decoder A;
see
Figure 28
analog ground reference for video decoder A
do not connect; leave open
analog supply voltage for the internal Clock Generation Circuit
(CGC) of video decoder A
analog ground for the internal CGC of video decoder A
analog ground for analog supply of the ADC of video decoder A
analog supply voltage for the ADC (3.3 V) of video decoder A
do not connect; leave open
do not connect; leave open
do not connect; leave open
analog ground reference for video decoder A
do not connect; leave open
do not connect; leave open
analog supply voltage for the internal CGC of video decoder A
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 16 January 2006
5 of 63
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