TDA7571
STPDACsw - Fully digital high efficiency power audio amplifier
Features
■
■
■
■
■
■
■
■
■
■
■
■
■
■
Output power 2 x 70W / 1 x 250W @ THD<1%
I
2
S input (F
S
= 38 to 48kHz)
PWM output (F
PWM
= F
S
x 8)
MCLK input = 256 x F
S
Operation on 24bit
±30V supply voltage (Max.)
St-by
Mute
Stereo/bridge operation selection
Protections against short circuit across the load
Chip thermal protection
External temperature sensor possibility
Thermal warning pins
Adjustable clip detector pin
The maximum output current and voltage swing
are depending by the output circuitry (power
supply, external power transistors and sensing
resistors). The device can work as a stereo
single-ended channels or a mono bridge power
amplifier.
HiQUAD-64
Description
The TDA7571 i is a fully digital switchmode power
audio amplifier with I
2
S digital input and PWM
output.
Table 1.
Device summary
Order code
TDA7571
Package
HiQUAD-64
Packing
Tray
September 2007
Rev 1
1/21
www.st.com
21
Contents
TDA7571
Contents
1
2
3
Block and simplified application diagram . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1
3.2
3.3
3.4
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Notes on the electrical schematic shown in
Figure 3
and
4
. . . . . . . . . . . 13
3.4.1
Main characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4
Functions, pins and components description . . . . . . . . . . . . . . . . . . . 14
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
Short circuit protection current calculation . . . . . . . . . . . . . . . . . . . . . . . . 14
External thermal protection network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Internal thermal protection network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Gate driving network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Dither . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
External connections description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.8.1
4.8.2
4.8.3
4.8.4
4.8.5
4.8.6
4.8.7
4.8.8
CD, THWEXT, THWINT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
MUTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
ST-BY - St-By pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
+Vs-low - . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
DATA, SEL, SCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
MCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
BRIDGE and L/R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.9
Components with critical placement and type . . . . . . . . . . . . . . . . . . . . . 18
5
6
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2/21
TDA7571
Block and simplified application diagram
1
Figure 1.
Block and simplified application diagram
Block and simplified application diagram
R9
C1
L/R BRIDGE
MCLK
MASTER CLOCK
SD DATA
WS WORD SEL
SCK CLOCK
R10 RFS
SGND
PGND
46
48
49
50
CHANNEL LEFT
HSD+
PROTECTIONS
INTERFACE
22
CHANNEL LEFT
LSD+
PROTECTIONS
21
23
34
33
R8
C7
Feed Lin
40
28
+Vs-Vref1
9
12
+Vs
42
+Vs-low
13
14
I2S
LEFT
DIGITAL
SIGNAL
PROCESSING
OSC
10
29
30
31
24
6
15
37
36
38
NTC
ST-BY
DGND
C3
MUTE
F
2.5V
-2.5V
SGND C4
DGND
56
55
REF
39
54
52
32
P/O
41
D1
43
D2
44
t1
45
t2
47
SGND
53
Feed Rin
57
-Vs+Vrefl
25
26,27,58,59
-Vs
C5
D01AU1271A
THERMA
L
PROTECTIONS
5V dig
Spl1
Spl2
+25V
R7
18
17
Gpl
Gpls
Gnls
Gnl
Snl2
Snl1
+Vs-5
-Vs+5
Spr1
Spr2
Gpr
Gprs
Gnrs
Gpr
Snr2
R4
61
60
-Vs+Vrefr
Snr1
M4
OUTPUT
LOWPASS
FILTER
M3
35
OUT
LEFT
CD SEL1
CD SEL2
CD
R6
-25V
CLIP
5V DIG
THW EXT
R1
THW INT
C2
NTC
8
7
CHANNEL RIGHT
HSD+
PROTECTIONS
4
5
63
RIGHT
DIGITAL
SIGNAL
PROCESSING
INTERFACE
CHANNEL RIGHT 64
LSD+
62
PROTECTIONS
+25V
R5
M2
OUTPUT
LOWPASS
FILTER
M1
OUT
RIGHT
-25V
5V
R2
R3
3/21
Pin description
TDA7571
2
Pin description
Figure 2.
Pins connection diagram (top view)
-Vs+Vrefr
Feed R in
ST-BY
MUTE
+2.5V
Gnrs
Snr2
Snr1
sgnd
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
21 22 23 24 25 26
-Vs
Gnls
Gnl
Snl2
Snl1
-Vs+Vrefl
27 28 29 30 31 32
-Vs
Feed L in
CDsel1
CDsel2
CD
dgnd
Gnr
-Vs
64 63 62 61 60 59
N.C.
N.C.
N.C.
Gpr
Gprs
+Vs-5
Spr2
Spr1
+Vs-Vref1
pgnd
N.C.
+Vs
Spl1
Spl2
-Vs+5
N.C.
Gpls
Gpl
N.C.
N.C.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
58 57 56 55 54 53
-2.5V
N.C.
SCK
WS
SD
t2
MCLK
t1
d2
d1
+Vs-low
P/O
5Vdig
f
NTC
THWext
THWint
Rfs
L/R
bridge
-Vs
AC00242
Table 2.
Pin
number
1
2
3
4
5
6
7
8
9
10
11
Pins description
Name
N.C.
N.C.
N.C.
Gpr
Gprs
+Vs-5
Spr2
Spr1
+Vs-Vref1
pgnd
N.C.
Sensing 2 PMOS, right channel
Sensing 1 PMOS, right channel
Supply drivers PMOS
Power ground
Not connected
+Vs-12V
0 (ref.)
Not connected
Not connected
Not connected
Gate PMOS, right channel
Sense gate PMOS, right channel
+Vs-12V
+Vs-12V
+Vs-6
30V
30V
30V
30V
30V
Function
Voltage limit
(low)
Voltage limit
(high)
4/21
TDA7571
Table 2.
Pin
number
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Pin description
Pins description (continued)
Name
+Vs
Spl1
Spl2
-Vs+5
N.C.
Gpls
Gpl
N.C.
N.C.
Gnl
Gnls
Snl2
Snl1
-Vs+Vrefl
-Vs
-Vs
Feed L in
CDsel1
CD sel2
CD
dgnd
bridge
L/R
Rfs
THWint
THWext
NTC
f
5Vdig
P/O
+Vs-low
d1
d2
Digital 5V supply output
PLL/FREE running osc. option
Positive voltage supply low power
Dither 1
Dither 2
Not connected
Sense gate PMOS, left channel
Gate PMOS, left channel
Not connected
Not connected
Gate NMOS, left channel
Gate NMOS, left channel
Sensing 2 NMOS, left channel
Sensing 1 NMOS, left Channel
Supply drivers NMOS. left channel
Negative power supply
Negative power supply
Feedback network left channel
Clip detector selection 1
Clip detector selection 2
Clip detector output
Digital ground
Stereo / bridge selection pin
0 = Stereo; 1 = Bridge
Bridge Left/Right Selection
1 = Right; 0 = Left
pcm-pwm gain conversion resistor
Internal thermal warning output
External thermal warning output
Sensing resistors network
0 (ref)
6V
6V
6V
5.5V
5.5V
5.5V
6V
6V
6V
30
6V
6V
-30V
-30V
-30V
-30V
-30V
-30V
-30V
-5V
5V
5.5V
5.5V
5.5V
-Vs+12V
-Vs+12V
-Vs+12V
+Vs-12V
+Vs-12V
30V
30V
Function
Positive power supply
Sensing 1 PMOS, left channel
Sensing 2 PMOS, left channel
Voltage limit
(low)
Voltage limit
(high)
30V
30V
30V
-Vs+6
5/21
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
