750kHz – 800MHz Low Phase Noise Multiplier VCXO
Universal Low Phase Noise IC’s
FEATURES
Selectable 750kHz to 800MHz range.
Low phase noise output (@ 10kHz frequency off-
set, -142dBc/Hz for 19.44MHz, -125dBc/Hz for
155.52MHz, -115dBc/Hz for 622.08MHz).
LVCMOS (PLL502-37), LVPECL (PLL502-35 and
PLL502-38) or LVDS (PLL502-39) output.
12MHz to 25MHz crystal input.
No external load capacitor or varicap required.
Output Enable selector.
Wide pull range (±200 ppm)
Selectable /16 to x32 frequency divider/multiplier.
3.3V operation.
Available in 16-Pin TSSOP or 16-pin 3x3mm QFN
GREEN/RoHS compliant packages.
PIN CONFIGURATION
(Top View)
VDD
XIN
XOUT
SEL3^
SEL2^
OE
VCON
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SEL0^
SEL1^
GND
CLKC
VDD
CLKT
GND
GND
TSSOP-16L
SEL0^ / VDD*
10
The PLL502-35 (LVPECL with inverted OE), PLL502-
37 (LVCMOS), PLL502-38 (LVPECL), and PLL502-39
(LVDS) are high performance and low phase noise
VCXO IC chips. They provide phase noise perform-
ance as low as –125dBc at 10kHz offset (at 155MHz),
by multiplying the input crystal frequency up to 32x.
The wide pull range (±200 ppm) and very low jitter
make them ideal for a wide range of applications, in-
cluding SONET/SDH and FEC. They accept funda-
mental parallel resonant mode crystals from 12MHz to
25MHz.
VDD / GND*
DESCRIPTION
XOUT
SEL3^
SEL2^
OE
13
14
15
16
12
11
SEL1^
9
XIN
8
7
6
5
GND
CLKC
VDD
CLKT
P502-3x
1
2
3
4
VCON
GND
GND
BLOCK DIAGRAM
SEL[3:0]
OE
VCON
XIN
XOUT
Oscillator
Amplifier
w/
integrated
varicaps
PLL
(Phase
Locked
Loop)
^:
*:
QFN-16L
Internal pull-up
On 3x3 package, PLL502-35/-38 do not have SEL0 available: Pin 10
is VDD, pin 11 is GND. However, PLL502-37/-39 have SEL0 (pin
10), and pin11 is VDD. See pin assignment table for details.
CLKC
CLKT
OUTPUT ENABLE LOGICAL LEVELS
Part #
PLL502-38
OE
0 (Default)
1
0
1 (Default)
State
Output enabled
Tri-state
Tri-state
Output enabled
PLL by-pass
PLL502-3x
PLL502-35
PLL502-37
PLL502-39
OE input: Logical states defined by LVPECL levels for PLL502-38
Logical states defined by LVCMOS levels for PLL502-37/-39
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 9/23/08 Page 1
GND
750kHz – 800MHz Low Phase Noise Multiplier VCXO
Universal Low Phase Noise IC’s
FREQUENCY SELECTION TABLE
SEL3
0
0
0
1
1
1
1
1
1
1
SEL2
0
1
1
0
0
0
1
1
1
1
SEL1
1
1
1
0
1
1
0
0
1
1
SEL0
1
0
1
1
0
1
0
1
0
1
Selected Multiplier
Fin x 32
Fin / 8
Fin x 2
Fin / 2
Fin / 16
Fin x 4
Fin / 4
Fin x 8
Fin x 16
No multiplication
Note:
SEL0 is not available (always “1”) for PLL502-35 and PLL502-38 in 3x3mm package
PIN DESCRIPTIONS PLL502-35 and PLL502-38 (see next page for PLL502-37/-39)
Name
XIN
XOUT
OE
VCON
GND
CLKT
CLKC
SEL0
SEL1
SEL2
SEL3
VDD
TSSOP
Pin number
2
3
6
7
8,9,10,14
11
13
16
15
5
4
1, 12
3x3mm QFN
Pin number
12
13
16
1
2,3,4,8,11
5
7
Not available
9
15
14
6,10
Type
I
I
I
I
P
O
O
I
I
I
I
P
+3.3V power supply.
Multiplier selector pins. These pins have an internal pull-
up that will default SEL to ‘1’ when not connected to
GND.
Description
Crystal input (See Crystal Specification on page 4)
Crystal output (See Crystal Specification on page 4)
Output enable pin (See OE logic state table on page 1)
Voltage Control input
Ground connection
LVPECL True output
LVPECL Complementary output
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 9/23/08 Page 2
750kHz – 800MHz Low Phase Noise Multiplier VCXO
Universal Low Phase Noise IC’s
PIN DESCRIPTIONS PLL502-37/-39 (see previous page for PLL502-35/-38)
Name
XIN
XOUT
OE
VCON
GND
CLKT
CLKC
SEL0
SEL1
SEL2
SEL3
VDD
TSSOP
Pin number
2
3
6
7
8,9,10,14
11
13
16
15
5
4
1, 12
3x3mm QFN
Pin number
12
13
16
1
2,3,4,8
5
7
10
9
15
14
6,11
Type
I
I
I
I
P
O
O
I
I
I
I
P
+3.3V power supply.
Multiplier selector pins. These pins have an internal pull-
up that will default SELx to ‘1’ when not connected to
GND.
Description
Crystal input. See Crystal Specification on page 4.
Crystal output. See Crystal Specification on page 4.
Output enable pin (see OE logic state table on page 1).
Voltage Control input.
Ground.
LVDS True output for PLL502-39
No Connect for PLL502-37
LVDS Complementary output for PLL502-39
LVCMOS out for PLL502-37
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
Supply Voltage
Input Voltage, dc
Output Voltage, dc
Storage Temperature
Ambient Operating Temperature*
Junction Temperature
Lead Temperature (soldering, 10s)
ESD Protection, Human Body Model
SYMBOL
V
DD
V
I
V
O
T
S
T
A
T
J
-0.5
-0.5
-65
-40
MIN.
MAX.
4.6
V
DD
+0.5
V
DD
+0.5
150
85
125
260
2.5
UNITS
V
V
V
C
C
C
C
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
*
Note:
Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 9/23/08 Page 3
750kHz – 800MHz Low Phase Noise Multiplier VCXO
Universal Low Phase Noise IC’s
2. Crystal Specifications
PARAMETERS
Crystal Resonator Frequency
Crystal Loading Rating
Crystal Pullability
Recommended ESR
SYMBOL
F
XIN
C
L (xtal)
C
0
/C
1 (xtal)
R
E
CONDITIONS
Parallel Fundamental Mode
At VCON = 1.65V
AT cut
AT cut
MIN.
12
9.5
250
30
TYP.
MAX.
25
UNITS
MHz
pF
-
Ω
Note:
Crystal Loading rating: 9.5pF is the loading the crystal sees from the VCXO chip at VCON = 1.65V. It is assumed that the crystal will be at nomi-
nal frequency at this load. If the crystal requires more load to be at nominal frequency, the additional load must be added externally. This however
may reduce the pull range.
3. Voltage Control Crystal Oscillator
PARAMETERS
VCXO Stabilization Time *
VCXO Tuning Range
CLK output pullability
VCXO Tuning Characteristic
Pull range linearity
VCON pin input impedance
VCON modulation BW
0V
VCON
3.3V, -3dB
2000
10
SYMBOL
T
VCXOSTB
CONDITIONS
From power valid
F
XIN
= 12 – 25MHz;
XTAL C
0
/C
1
< 250
0V
VCON
3.3V
VCON=1.65V,
1.65V
200
150
10
500
MIN.
TYP.
MAX.
10
UNITS
ms
ppm
ppm
ppm/V
%
kΩ
kHz
Note:
Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits.
4. General Electrical Specifications
PARAMETERS
Supply Current,
Dynamic (with
Loaded Outputs)
Operating
Voltage
Output Clock
Duty Cycle
Short Circuit
Current
SYMBOL
I
DD
CONDITIONS
LVPECL/LVDS/
24MHz< F
OUT
<96MHz
LVCMOS
96MHz< F
OUT
<800MHz
2.97
@ 50% V
DD
(LVCMOS)
@ 1.25V (LVDS)
@ V
DD
– 1.3V (LVPECL)
45
45
45
50
50
50
50
F
OUT
<24MHz
MIN.
TYP.
MAX.
60/28/15
65/45/30
100/80/40
3.63
55
55
55
V
%
mA
mA
UNITS
V
DD
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 9/23/08 Page 4
750kHz – 800MHz Low Phase Noise Multiplier VCXO
Universal Low Phase Noise IC’s
5. Jitter Specifications
PARAMETERS
CONDITIONS
With capacitive decoupling
between V
DD
and GND.
Over 10,000 cycles.
FREQUENCY
19.44MHz
Period jitter RMS
77.76MHz
155.52MHz
622.08MHz
19.44MHz
Period jitter
Peak-to-Peak
With capacitive decoupling
between V
DD
and GND.
Over 10,000 cycles.
77.76MHz
155.52MHz
622.08MHz
Integrated jitter RMS
Integrated 12kHz to 20MHz
155.52MHz
622.08MHz
MIN.
TYP.
2.2
4.5
4.5
5.0
17
25
27
35
2.5
2.5
4
4
ps
ps
ps
MAX.
UNITS
6. Phase Noise Specifications
PARAMETERS
FREQUENCY
19.44MHz
Phase Noise relative
to carrier (typical)
77.76MHz
155.52MHz
622.08MHz
Note: Phase Noise measured at VCON = 0V
@10Hz
-80
-72
-65
-55
@100Hz
-108
-103
-95
-85
@1kHz
-132
-122
-120
-109
@10kHz
-142
-130
-125
-115
@100kHz
-150
-125
-121
-110
UNITS
dBc/Hz
7. LVCMOS Electrical Characteristics
PARAMETERS
Output drive current
Output Clock Rise/Fall Time
SYMBOL
I
OH
I
OL
CONDITIONS
V
OH
= V
DD
-0.4V, V
DD
=3.3V
V
OL
= 0.4V, V
DD
= 3.3V
0.3V ~ 3.0V with 15 pF load
MIN.
10
10
2.4
TYP.
MAX.
UNITS
mA
mA
ns
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 9/23/08 Page 5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
