873991
L
OW
V
OLTAGE
, LVCMOS/
LVPECL-
TO
-LVPECL/ECL C
LOCK
G
ENERATOR
G
ENERAL
D
ESCRIPTION
The 873991 is a low voltage, low skew, 3.3V LVPECL
or ECL Clock Generator . The 873991 has two selectable
clock inputs. The PCLK, nPCLK pair can accept an LVPECL
input and the TEST_CLK pin can accept a LVCMOS or LVT-
TL input. This device has a fully integrated PLL along with
frequency configurable outputs. An external feedback input and
output regenerates clocks with “zero delay”.
The four independent banks of outputs each have their
own output dividers, which allow the device to generate a
multitude of different bank frequency ratios and output-to-
input frequency ratios. The output frequency range is 25MHz to
400MHz and the input frequency range is 6.25MHz to 125MHz.
The PLL_SEL input can be used to bypass the PLL for test
and system debug purposes. In bypass mode, the input clock
is routed around the PLL and into the internal output dividers.
The 873991 also has a SYNC output which can be used for
system synchronization purposes. It monitors Bank A and Bank
C outputs for coincident rising edges and signals a pulse per the
timing diagrams in this data sheet. This feature is used primarily
in applications where Bank A and Bank C are running at different
frequencies, and is particularly useful when they are running at
non-integer multiples of each other.
Example Applications:
1. Line Card Multiplier: Multiply 19.44MHz from a back-plane
to 77.76MHz on the line card ASIC and Serdes.
2. Zero Delay Buffer: Fan out up to thirteen 100MHz copies
from a reference clock to multiple processing units on an
embedded system.
F
EATURES
•
14 differential LVPECL outputs
•
Selectable differential LVPECL or TEST_CLK inputs
•
PCLK, nPCLK can accept the following input levels:
LVPECL, CML, SSTL
•
TEST_CLK accepts the following input levels:
LVCMOS, LVTTL
•
Input frequency range: 6.25MHz to 125MHz
•
Output frequency: 400MHz (maximum)
•
VCO range: 200MHz to 800MHz
•
Output skew: 250ps (maximum)
•
Cycle-to-cyle jitter: ±50ps (typical)
•
LVPECL mode operating voltage supply range:
V
CC
= 3.135V to 3.465V, V
EE
= 0V
•
ECL mode operating voltage supply range:
V
CC
= 0V, V
EE
= -3.465V to -3.135V
•
0°C to 70°C ambient operating temperature
•
Industrial temperature available upon request
•
Lead-Free package fully RoHS compliant
•
Use replacement part 873996AYLF
P
IN
A
SSIGNMENT
52-Lead LQFP
10mm x 10mm x 1.4mm package body
Y package
Top View
873991
www.idt.com
1
REV. A 8/25/15
873991
L
OW
V
OLTAGE
, LVCMOS/
LVPECL-
TO
-LVPECL/ECL C
LOCK
G
ENERATOR
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
Name
V
EE
MR
Power
Input
Type
Description
Negative supply pin.
Active High Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs (Qx) to go low and the inverted outputs
Pulldown
(nQx) to go high. When logic LOW, the internal dividers and the outputs
are enabled. LVCMOS/LVTTL interface levels.
PLL enable pin. When logic LOW, PLL is enabled. When logic HIGH, PLL
Pulldown
is in bypass mode. LVCMOS/LVTTL interface levels.
Selects between the different reference inputs as the PLL reference
Pulldown source. When logic LOW, selects PCLK/nPCLK. When logic HIGH, selects
TEST_CLK. LVCMOS/LVTTL interface levels.
Pulldown Feedback frequency select pins. LVCMOS/LVTTL interface levels.
Pulldown LVCMOS/LVTTL test clock input.
Pulldown Non-inverting differential LVPECL clock input.
Pullup/
Inverting differential LVPECL clock input. V
CC
/2 default when left floating.
Pulldown
Core supply pin.
Pulldown External feedback input.
Pullup/
External feedback input. t. V
CC
/2 default when left floating.
Pulldown
Analog supply pin.
Differential feedback output pair. LVPECL Interface levels.
Output supply pins.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Pulldown Frequency select pins. LVCMOS/LVTTL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Pulldown
SYNC output select pin. When LOW, the SYNC otuput follows the timing
diagram (page 5). When HIGH, QD output follows QC output.
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17, 22, 30, 42
18, 19
20, 21
23, 24
25, 26
27
33
36
39
28, 29
31, 32
34, 35
37, 38
40, 41
43, 44
45, 46
47, 48
49, 50
51
52
PLL_EN
REF_SEL
FSEL_FB2
FSEL_FB1
FSEL_FB0
TEST_CLK
PCLK
nPCLK
V
CC
EXT_FB
nEXT_FB
V
CCA
nQFB
QFB
V
CCO
nQD0, QD0
nQD1, QD1
nQC0, QC0
nQC1, QC1
FSEL3
FSEL2
FSEL1
FSEL0
nQC2, QC2
nQB0, QB0
nQB1, QB1
nQB2, QB2
nQB3, QB3
nQA0, QA0
nQA1, QA1
nQA2, QA2
nQA3, QA3
SYNC_SEL
VCO_SEL
Input
Input
Input
Input
Input
Input
Power
Input
Input
Power
Output
Power
Output
Output
Output
Output
Input
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input
Pulldown Selects VCO range. LVCMOS/LVTTL interface levels.
www.idt.com
3
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
873991
REV. A 8/25/15
模拟电子
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