TS4855
LOUDSPEAKER & HEADSET DRIVER
WITH VOLUME CONTROL
s
s
s
s
s
s
s
s
s
s
OPERATING FROM V
CC
= 3.0 V to 5.0 V
SPEAKER: Mono, THD+N @ 1 kHz is 1%
Max @ 1 W into 8
Ω
BTL
HEADSET: Stereo, THD+N @ 1 kHz is 0.5%
Max. @ 85 mW into 32
Ω
BTL
VOLUME CONTROL: 32-step digital
volume control
OUTPUT MODE: Eight different selections
Ultra low pop-and-click
Low Shutdown Current (0.1 µA, typ.)
Thermal Shutdown Protection
FLIP-CHIP Package 18 X 300 µm Bumps
TS4855E IJT Lead-Free option available
TS4855IJT - Flip Chip
PIN CONNECTIONS
(top view)
DESCRIPTION
The TS4855 is a complete low power audio
amplifier solution targeted at mobile phones. It
integrates, into an extremely compact flip-chip
package, an audio amplifier, a speaker driver, and
a headset driver.
The Audio Power Amplifier can deliver 1.1 W
(typ.) of continuous RMS output power into an 8
Ω
speaker with a 1% THD+N value. To the headset
driver, the amplifier can deliver 85 mW (typ.) per
channel of continuous average power into stereo
32
Ω
bridged-tied load with 0.5% THD+N @ 5 V.
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Pin Out
(top view)
This device features a 32-step digital volume
control and 8 different output selections. The
digital volume and output modes are controlled
through a three-digit SPI interface bus.
APPLICATIONS
Mobile Phones
ORDER CODE
Part Number
TS4855IJT
TS4855EIJT
Temperature
Range
-40, +85°C
-40, +85°C
Package
J
•
•
1/27
J =
Flip Chip Package - only available in Tape & Reel (JT))
March 2004
TS4855
1
Application Information for a Typical Application
APPLICATION INFORMATION FOR A TYPICAL APPLICATION
bs
O
External component descriptions
Component
C
in
C
s
C
B
Functional Description
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This is the input coupling capacitor. It blocks the DC voltage at, and couples the input signal to the
amplifier’s input terminals. Cin also creates a highpass filter with the internal input impedance Zin at
Fc = 1 / (2
π
x Zin x Cin).
This is the Supply Bypass capacitor. It provides power supply filtering.
This is the Bypass pin capacitor. It provides half-supply filtering.
2/27
SPI Bus Interface
2
SPI BUS INTERFACE
TS4855
2.1 Pin Descriptions
Pin
DATA
CLK
ENB
This is the serial data input pin
This is the clock input pin
This is the SPI enable pin active at high level
Functional Description
2.2 SPI Operation Description
The serial data bits are organized into a field
containing 8 bits of data as shown in
Table 1.
The
DATA 0 to DATA 2 bits determine the output
mode of the TS4855 as shown in
Table 2.
The
DATA 3 to DATA 7 bits determine the gain level
setting as illustrated by
Table 3.
For each SPI
transfer, the data bits are written to the DATA pin
with the least significant bit (LSB) first. All serial
data are sampled at the rising edge of the CLK
signal. Once all the data bits have been sampled,
ENB transitions from logic-high to logic low to
complete the SPI sequence. All 8 bits must be
received before any data latch can occur. Any
excess CLK and DATA transitions will be ignored
after the height rising clock edge has occurred.
For any data sequence longer than 8 bits, only the
first 8 bits will get loaded into the shift register and
the rest of the bits will be disregarded.
Table 1: Bit Allocation
DATA
LSB
DATA 0
Output
Mode #
0
bs
O
1
2
3
4
5
6
7
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DATA 2
0
0
0
0
1
1
1
1
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0
0
1
1
0
0
1
1
)-
(s
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DATA 1
DATA 2
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MODES
Mode 1
Mode 2
Mode 3
gain 1
gain 2
gain 3
gain 4
gain 5
DATA 3
DATA 4
DATA 5
DATA 6
MSB
DATA 7
Table 2: Output Mode Selection
DATA 0
0
1
0
1
0
1
0
1
SPKR
out
SD
+12dBxP
IHF
MUTE
+12dBxP
IHF
MUTE
+12dBxP
IHF
MUTE
+12dBxP
IHF
R
out
SD
SD
G1xP
HS
G1xP
HS
G2xR
in
G2xR
in
G1xP
HS
+
G2xR
in
G1xP
HS
+
G2xR
in
L
out
SD
SD
G1xP
HS
G1xP
HS
G2xL
in
G2xL
in
G1xP
HS
+
G2xL
in
G1xP
HS
+
G2xL
in
DATA 1
(SD = Shut Down Mode,
P
HS
= Non Filtered Phone In HS, P
IHF
= External High Pass Filtered Phone In IHF)
3/27
TS4855
Table 3: Gain Control Settings
G2: Gain (dB)
-34.5
-33.0
-31.5
-30.0
-28.5
-27.0
-25.5
-24.0
-22.5
-21.0
-19.5
-18.0
-16.5
-15.0
-13.5
-12.0
-10.5
-9.0
-7.5
-6.0
-4.5
-3.0
-1.5
0.0
1.5
3.0
4.5
6.0
7.5
9.0
10.5
12.0
G1: Gain (dB)
-40.5
-39.0
-37.5
-36.0
-34.5
-33.0
-31.5
-30.0
-28.5
-27.0
-25.5
-24.0
-22.5
-21.0
-19.5
-18.0
-16.5
-15.0
-13.5
-12.0
DATA 7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DATA 6
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
DATA 5
0
0
0
0
1
1
1
1
0
0
0
SPI Bus Interface
DATA 4
0
0
1
1
0
0
1
1
0
DATA 3
0
1
0
1
0
1
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-10.5
-9.0
-7.5
-6.0
-4.5
-3.0
-1.5
0.0
1.5
3.0
4.5
6.0
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1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
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-
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
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1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
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0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
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0
0
1
1
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0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
4/27
Absolute Maximum Ratings
2.3 SPI Timing Diagram
TS4855
3
ABSOLUTE MAXIMUM RATINGS
Parameter
Supply voltage
1
Storage Temperature
Symbol
V
CC
T
oper
T
stg
T
j
R
thja
Pd
ESD
ESD
Operating Free Air Temperature Range
Maximum Junction Temperature
Flip Chip Thermal Resistance Junction to Ambient
2
Power Dissipation
Human Body Model
3
Machine Model
4
Latch-up Immunity
Lead Temperature (soldering, 10sec)
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4
1) All voltage values are measured with respect to the ground pin.
2) Device is protected in case of over temperature by a thermal shutdown active @ 150°C typ.
3) Human body model, 100pF discharged through a 1.5
k
Ω
resistor into pin of device.
4) This is a minimum Value. Machine model ESD, a 200pF cap is charged to the specified voltage, then discharged directly into the IC with no external
series resistor (internal resistor < 5Ω), into pin to pin of device.
5.) All PSRR data limits are guaranteed by evaluation tests.
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Value
6
-40 to + 85
-65 to +150
150
166
Internally Limited
2
100
200
250
Unit
V
°C
°C
°C
°C/W
kV
V
mA
°C
OPERATING CONDITIONS
Parameter
Supply Voltage
Maximum Phone In Input Voltage
Thermal Shutdown Temperature
Value
3 to 5
G
ND
to V
CC
G
ND
to V
CC
150
Unit
V
V
V
°C
Symbol
V
CC
V
phin
T
SD
V
Rin/
V
Lin
Maximum Rin & Lin Input Voltage
5/27
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