December 2007
HY[B/I]18T256400A[C/F](L)
HY[B/I]18T256800A[C/F](L)
HY[B/I]18T256160A[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
DDR2 SDRAM
RoHS Compliant Products
Internet Data Sheet
Rev. 1.50
Internet Data Sheet
HY[B/I]18T256[40/80/16]0A[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
HY[B/I]18T256400A[C/F](L), HY[B/I]18T256800A[C/F](L), HY[B/I]18T256160A[C/F](L)
Revision History: 2007-12, Rev. 1.50
Page
All
All
All
All
Subjects (major changes since last revision)
Adapted Internet Version
25 New Products added
Editorial Changes
Qimonda update
Added low-power components HYB18T256[40/80/16]0AFL-3.7
Added DDR2-800 5-5-5 components
92
Chapter 2
Updated
I
DD
Currents (
I
DD2P
,
I
DD3P1
,
I
DD6
)
Updated Pin Configuration - various editorial changes on notes
Previous Revision: 2007-01 Rev. 1.41
Previous Revision: 2005-07 Rev. 1.4
Previous Revision: 2005-07 Rev. 1.3
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
techdoc@qimonda.com
qag_techdoc_rev411 / 3.31 QAG / 2007-01-22
03062006-7M17-PXBC
2
Internet Data Sheet
HY[B/I]18T256[40/80/16]0A[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
1
Overview
This chapter gives an overview of the 256-Mbit Double-Data-Rate-Two SDRAM product family and describes its main
characteristics.
1.1
Features
The 256-Mbit Double-Data-Rate-Two SDRAM offers the following key features:
• Off-Chip-Driver impedance adjustment (OCD) and
• 1.8 V
±
0.1 V Power Supply
1.8 V
±
0.1 V (SSTL_18) compatible I/O
On-Die-Termination (ODT) for better signal quality
• DRAM organizations with 4,8,16 data in/outputs
• Auto-Precharge operation for read and write bursts
• Double Data Rate architecture:
• Auto-Refresh, Self-Refresh and power saving Power-
– two data transfers per clock cycle
Down modes
– four internal banks for concurrent operation
• Average Refresh Period 7.8
μs
at a
T
CASE
lower
• Programmable CAS Latency: 3, 4, 5 and 6
than 85 °C, 3.9
μs
between 85 °C and 95 °C
• Programmable Burst Length: 4 and 8
• Programmable self refresh rate via EMRS2 setting
• Differential clock inputs (CK and CK)
• Programmable partial array refresh via EMRS2 settings
• Bi-directional, differential data strobes (DQS and DQS) are
• DCC enabling via EMRS2 setting
• Full and reduced Strength Data-Output Drivers
transmitted / received with data. Edge aligned with read
• 1KB page size
data and center-aligned with write data.
• Packages: PG-TFBGA-84, PG-TFBGA-60, P-TFBGA-84,
• DLL aligns DQ and DQS transitions with clock
P-TFBGA-60
• DQS can be disabled for single-ended data strobe
• RoHS Compliant Products
1)
operation
• All Speed grades faster than DDR2–400 comply with
• Commands entered on each positive clock edge, data and
DDR2–400 timing specifications when run at a clock rate
data mask are referenced to both edges of DQS
• Data masks (DM) for write data
of 200 MHz.
• Posted CAS by programmable additive latency for better
command and data bus efficiency
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Rev. 1.50, 2007-12
03062006-7M17-PXBC
3
Internet Data Sheet
HY[B/I]18T256[40/80/16]0A[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
TABLE 1
Performance Table
QAG Speed Code
DRAM Speed Grade
CAS-RCD-RP latencies
Max.
Clock Frequency
CL3
CL4
CL5
CL6
Min. RAS-CAS-Delay
Min. Row Precharge
Time
Min. Row Active Time
Min. Row Cycle Time
Precharge-All (4 banks)
command period
DDR2
–25F
–800D
5–5–5
–2.5
–800E
6–6–6
200
266
333
400
15
15
45
60
15
–3
–667C
4–4–4
200
333
333
–
12
12
45
57
12
–3S
–667D
5–5–5
200
266
333
–
15
15
45
60
15
–3.7
–533C
4–4–4
200
266
266
–
15
15
45
60
15
–5
–400B
3–3–3
200
200
–
–
15
15
40
55
15
Unit
Note
t
CK
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
f
CK3
f
CK4
f
CK5
f
CK6
t
RCD
t
RP
t
RAS
t
RC
t
PREA
200
266
400
–
12.5
12.5
45
57.5
12.5
1.2
Description
latched at the cross point of differential clocks (CK rising and
CK falling). All I/Os are synchronized with a single ended
DQS or differential DQS-DQS pair in a source synchronous
fashion.
A 15 bit address bus for
×4
and
×8
organised components
and a 15 bit address bus for
×16
components is used to
convey row, column and bank address information in a RAS-
CAS multiplexing style.
A 15 bit address bus is used to convey row, column and bank
address information in a RAS-CAS multiplexing style.
The DDR2 device operates with a 1.8 V
±
0.1 V power
supply. An Auto-Refresh and Self-Refresh mode is provided
along with various power-saving power-down modes.
The functionality described and the timing specifications
included in this data sheet are for the DLL Enabled mode of
operation.
The DDR2 SDRAM is available in TFBGA package.
The 256-Mbit DDR2 DRAM is a high-speed Double-Data-
Rate-Two CMOS Synchronous DRAM device containing
268,435,456 bits and internally configured as a quad-bank
DRAM. The 256-Mbit device is organized as 16 Mbit
×4
I/O
×4
banks or 8 Mbit
×8
I/O
×4
banks or 4 Mbit
×16
I/O
×4
banks
chip.
These synchronous devices achieve high speed transfer
rates starting at 400 Mb/sec/pin for general applications. See
Table 1
for performance figures.
The device is designed to comply with all DDR2 DRAM key
features:
1. Posted CAS with additive latency.
2. Write latency = read latency - 1.
3. Normal and weak strength data-output driver.
4. Off-Chip Driver (OCD) impedance adjustment.
5. On-Die Termination (ODT) function.
All of the control and address inputs are synchronized with a
pair of externally supplied differential clocks. Inputs are
Rev. 1.50, 2007-12
03062006-7M17-PXBC
4
Internet Data Sheet
HY[B/I]18T256[40/80/16]0A[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
TABLE 2
Ordering Information for RoHS Compliant Products
Product Type
1)
Org. Speed
CAS-RCD-RP
Latencies
2)3)4)
Clock (MHz) Package
Note
5)
Standard Temperature Range (0 °C - +85 °C)
DDR2-800E( 6-6-6)
HYB18T256400AF-2.5
HYB18T256160AF-2.5
DDR2-800D( 5-5-5)
HYB18T256800AF-25F
HYB18T256400AF-25F
HYB18T256160AF-25F
DDR2-667D( 5-5-5)
HYB18T256160AF-3S
HYB18T256800AF-3S
HYB18T256400AF-3S
DDR2-667C( 4-4-4)
HYB18T256160AF-3
DDR2-533C( 4-4-4)
HYB18T256160AFL-3.7
HYB18T256400AFL-3.7
HYB18T256800AFL-3.7
HYB18T256800AF-3.7
HYB18T256400AF-3.7
HYB18T256160AF-3.7
DDR2-533B( 3-3-3)
HYB18T256800AF-2.5
DDR2-400B( 3-3-3)
HYB18T256800AF-5
HYB18T256400AF-5
HYB18T256160AF-5
DDR2-667D( 5-5-5)
HYI18T256800AF-3S
HYI18T256160AF-3S
HYI18T256400AF-3S
DDR2-533C( 4-4-4)
HYI18T256160AF-3.7
HYI18T256800AF-3.7
×16
×8
DDR2-533C
DDR2-533C
4-4-4
4-4-4
266
266
PG-TFBGA-84
PG-TFBGA-60
×8
×16
×4
DDR2-667D
DDR2-667D
DDR2-667D
5-5-5
5-5-5
5-5-5
333
333
333
PG-TFBGA-60
PG-TFBGA-84
PG-TFBGA-60
×8
×4
×16
DDR2-400B
DDR2-400B
DDR2-400B
3-3-3
3-3-3
3-3-3
200
200
200
PG-TFBGA-60
PG-TFBGA-60
PG-TFBGA-84
×8
DDR2-533B
3-3-3
266
PG-TFBGA-60
×16
×4
×8
×8
×4
×16
DDR2-533C
DDR2-533C
DDR2-533C
DDR2-533C
DDR2-533C
DDR2-533C
4-4-4
4-4-4
4-4-4
4-4-4
4-4-4
4-4-4
266
266
266
266
266
266
PG-TFBGA-84
PG-TFBGA-60
PG-TFBGA-60
PG-TFBGA-60
PG-TFBGA-60
PG-TFBGA-84
×16
DDR2-667C
4-4-4
333
PG-TFBGA-84
×16
×8
×4
DDR2-667D
DDR2-667D
DDR2-667D
5-5-5
5-5-5
5-5-5
333
333
333
PG-TFBGA-84
PG-TFBGA-60
PG-TFBGA-60
×8
×4
×16
DDR2-800D
DDR2-800D
DDR2-800D
5-5-5
5-5-5
5-5-5
400
400
400
PG-TFBGA-60
PG-TFBGA-60
PG-TFBGA-84
×4
×16
DDR2-800E
DDR2-800E
6-6-6
6-6-6
400
400
PG-TFBGA-60
PG-TFBGA-84
Industrial Temperature Range (–40 °C - +85 °C)
Rev. 1.50, 2007-12
03062006-7M17-PXBC
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
