memories with clocked read and write interfaces. All are nine
bits wide. The CY7C4281/91 are pin-compatible to the
CY7C42X1 Synchronous FIFO family. Programmable
features include Almost Full/Almost Empty flags. These FIFOs
provide solutions for a wide variety of data buffering needs,
including high-speed data acquisition, multiprocessor inter-
faces, and communications buffering.
These FIFOs have nine-bit input and output ports that are
controlled by separate clock and enable signals. The input port
is controlled by a free-running clock (WCLK) and two
write-enable pins (WEN1, WEN2/LD).
When WEN1 is LOW and WEN2/LD is HIGH, data is written
into the FIFO on the rising edge of the WCLK signal. While
WEN1, WEN2/LD is held active, data is continually written into
the FIFO on each WCLK cycle. The output port is controlled in
a similar manner by a free-running read clock (RCLK) and two
read enable pins (REN1, REN2). In addition, the
CY7C4281/91 has an output enable pin (OE). The read
(RCLK) and write (WCLK) clocks may be tied together for
single-clock operation or the two clocks may be run indepen-
dently for asynchronous read/write applications. Clock
frequencies up to 100 MHz are achievable. Depth expansion
is possible using one enable input for system control, while the
other enable is controlled by expansion logic to direct the flow
of data.
Logic Block Diagram
D
0–8
Pin Configuration
PLCC
Top View
D
2
D
3
D
4
D
5
D
6
D
7
D
8
INPUT
REGISTER
WCLK WEN1 WEN2/LD
FLAG
PROGRAM
REGISTER
WRITE
CONTROL
EF
Dual Port
RAMARRAY
64K x 9
128K x 9
FLAG
LOGIC
PAE
PAF
FF
READ
POINTER
D
1
D
0
PAF
PAE
GND
REN1
RCLK
REN2
OE
5
6
7
8
9
10
11
12
13
4 3 2 1 32 31 30
29
28
25
24
23
22
21
14 15 16 17 18 19 20
EF
FF
Q
0
Q
1
Q
2
Q
3
Q
4
CY7C4281
CY7C4291
27
26
RS
WEN1
WCLK
WEN2/LD
V
CC
Q
8
Q
7
Q
6
Q
5
WRITE
POINTER
RS
RESET
LOGIC
THREE-STATE
OUTPUT REGISTER
OE
Q
0–8
READ
CONTROL
RCLK REN1 REN2
Cypress Semiconductor Corporation
Document #: 38-06007 Rev. *C
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised August 2, 2005
CY7C4281
CY7C4291
Pin Definitions
Signal Name
D
0–8
Q
0−8
WEN1
Description
Data Inputs
Data Outputs
Write Enable 1
I/O
I
O
I
Data Inputs for 9-bit bus.
Data Outputs for 9-bit bus.
The only write enable when device is configured to have programmable flags.
Data is written on a LOW-to-HIGH transition of WCLK when WEN1 is asserted and FF
is HIGH. If the FIFO is configured to have two write enables, data is written on a
LOW-to-HIGH transition of WCLK when WEN1 is LOW and WEN2/LD and FF are HIGH.
If HIGH at reset, this pin operates as a second write enable.
If LOW at reset, this
pin operates as a control to write or read the programmable flag offsets. WEN1 must be
LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written into
the FIFO if the FF is LOW. If the FIFO is configured to have programmable flags,
WEN2/LD is held LOW to write or read the programmable flag offsets.
Enables the device for Read operation.
Both REN1 and REN2 must be asserted to
allow a read operation.
The rising edge clocks data into the FIFO when WEN1 is LOW and WEN2/LD is
HIGH and the FIFO is not Full.
When LD is asserted, WCLK writes data into the
programmable flag-offset register.
The rising edge clocks data out of the FIFO when REN1 and REN2 are LOW and
the FIFO is not Empty.
When WEN2/LD is LOW, RCLK reads data out of the program-
mable flag-offset register.
When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
When PAE is LOW, the FIFO is almost empty based on the almost empty offset
value programmed into the FIFO.
PAE is synchronized to RCLK.
When PAF is LOW, the FIFO is almost full based on the almost full offset value
programmed into the FIFO.
PAF is synchronized to WCLK.
Resets device to empty condition.
A reset is required before an initial read or write
operation after power-up.
When OE is LOW, the FIFO’s data outputs drive the bus to which they are
connected.
If OE is HIGH, the FIFO’s outputs are in High Z (high-impedance) state.
CY7C4291
128k x 9
32-pin PLCC
Description
WEN2/LD
Dual Mode Pin
Write Enable 2
Load
I
REN1, REN2
WCLK
Read Enable
Inputs
Write Clock
I
I
RCLK
Read Clock
I
EF
FF
PAE
PAF
RS
OE
Empty Flag
Full Flag
Programmable
Almost Empty
Programmable
Almost Full
Reset
Output Enable
CY7C4281
O
O
O
O
I
I
Density
Package
64k x 9
32-pin PLCC
Selection Guide
7C4281/91-10
Maximum Frequency
Maximum Access Time
Minimum Cycle Time
Minimum Data or Enable Set-up
Minimum Data or Enable Hold
Maximum Flag Delay
Active Power Supply Current (I
CC1
)
Commercial
Industrial
100
8
10
3
0.5
8
40
45
7C4281/91-15
66.7
10
15
4
1
10
40
7C4281/91-25
40
15
25
6
1
15
40
Unit
MHz
ns
ns
ns
ns
ns
mA
Document #: 38-06007 Rev. *C
Page 2 of 16
CY7C4281
CY7C4291
Functional Description
(continued)
The CY7C4281/91 provides four status pins: Empty, Full,
Programmable Almost Empty, and Programmable Almost
Full. The Almost Empty/Almost Full flags are programmable to
single-word granularity. The programmable flags default to
Empty+7 and Full-7.
The flags are synchronous, i.e., they change state relative to
either the read clock (RCLK) or the write clock (WCLK). When
entering or exiting the Empty and Almost Empty states, the
flags are updated exclusively by the RCLK. The flags denoting
Almost Full and Full states are updated exclusively by WCLK.
The synchronous flag architecture guarantees that the flags
maintain their status for at least one cycle.
All configurations are fabricated using an advanced 0.5µ
CMOS technology. Input ESD protection is greater than
2001V, and latch-up is prevented by the use of guard rings.
Write Enable 1 (WEN1)
— If the FIFO is configured for
programmable flags, Write Enable 1 (WEN1) is the only write
enable control pin. In this configuration, when Write Enable 1
(WEN1) is LOW, data can be loaded into the input register and
RAM array on the LOW-to-HIGH transition of every write clock
(WCLK). Data is stored is the RAM array sequentially and
independently of any on-going read operation.
Write Enable 2/Load (WEN2/LD)
— This is a dual-purpose
pin. The FIFO is configured at Reset to have programmable
flags or to have two write enables, which allows for depth
expansion. If Write Enable 2/Load (WEN2/LD) is set active
HIGH at Reset (RS = LOW), this pin operates as a second
write enable pin.
If the FIFO is configured to have two write enables, when Write
Enable (WEN1) is LOW and Write Enable 2/Load (WEN2/LD)
is HIGH, data can be loaded into the input register and RAM
array on the LOW-to-HIGH transition of every write clock
(WCLK). Data is stored in the RAM array sequentially and
independently of any on-going read operation.
Architecture
The CY7C4281/91 consists of an array of 64K to 128K words
of nine bits each (implemented by a dual-port array of SRAM
cells), a read pointer, a write pointer, control signals (RCLK,
WCLK, REN1, REN2, WEN1, WEN2, RS), and flags (EF,
PAE, PAF, FF).
Programming
When WEN2/LD is held LOW during Reset, this pin is the load
(LD) enable for flag offset programming. In this configuration,
WEN2/LD can be used to access the four nine-bit offset
registers contained in the CY7C4281/4291 for writing or
reading data to these registers.
When the device is configured for programmable flags and
both WEN2/LD and WEN1 are LOW, the first LOW-to-HIGH
transition of WCLK writes data from the data inputs to the
empty offset least significant bit (LSB) register. The second,
third, and fourth LOW-to-HIGH transitions of WCLK store data
in the empty offset most significant bit (MSB) register, full
offset LSB register, and full offset MSB register, respectively,
when WEN2/LD and WEN1 are LOW. The fifth LOW-to-HIGH
transition of WCLK while WEN2/LD and WEN1 are LOW
writes data to the empty LSB register again.
Figure 1
shows
the registers sizes and default values for the various device
types.
64K × 9
8
7
Empty Offset (LSB) Reg.
Default Value = 007h
Resetting the FIFO
Upon power-up, the FIFO must be reset with a Reset (RS)
cycle. This causes the FIFO to enter the Empty condition
signified by EF being LOW. All data outputs (Q
0–8
) go LOW
t
RSF
after the rising edge of RS. In order for the FIFO to reset
to its default state, the user must not read or write while RS is
LOW. All flags are guaranteed to be valid t
RSF
after RS is taken
LOW.
FIFO Operation
When the WEN1 signal is active LOW, WEN2 is active HIGH,
and FF is active HIGH, data present on the D
0–8
pins is written
into the FIFO on each rising edge of the WCLK signal.
Similarly, when the REN1 and REN2 signals are active LOW
and EF is active HIGH, data in the FIFO memory will be
presented on the Q
0–8
outputs. New data will be presented on
each rising edge of RCLK while REN1 and REN2 are active.
REN1 and REN2 must set up t
ENS
before RCLK for it to be
a valid read function. WEN1 and WEN2 must occur t
ENS
before WCLK for it to be a valid write function.
An output enable (OE) pin is provided to three-state the Q
0–8
outputs when OE is asserted. When OE is enabled (LOW),
data in the output register will be available to the Q
0–8
outputs
after t
OE
. If devices are cascaded, the OE function will only
output data on the FIFO that is read enabled.
The FIFO contains overflow circuitry to disallow additional
writes when the FIFO is full, and underflow circuitry to disallow
additional reads when the FIFO is empty. An empty FIFO
maintains the data of the last valid read on its Q
0–8
outputs
even after additional reads occur.
128K× 9
0
8
7
Empty Offset (LSB) Reg.
Default Value = 007h
0
8 7
(MSB)
Default Value = 000h
0
8
(MSB)
Default Value = 000h
0
8 7
Full Offset (LSB) Reg
Default Value = 007h
0
8
7
Full Offset (LSB) Reg
Default Value = 007h
0
8 7
(MSB)
Default Value = 000h
0
8
(MSB)
Default Value = 000h
0
Figure 1. Offset Register Location and Default Values
Document #: 38-06007 Rev. *C
Page 3 of 16
CY7C4281
CY7C4291
It is not necessary to write to all the offset registers at one time.
A subset of the offset registers can be written; then by bringing
the WEN2/LD input HIGH, the FIFO is returned to normal read
and write operation. The next time WEN2/LD is brought LOW,
a write operation stores data in the next offset register in
sequence.
The contents of the offset registers can be read to the data
outputs when WEN2/LD is LOW and both REN1 and REN2
are LOW. LOW-to-HIGH transitions of RCLK read register
contents to the data outputs. Writes and reads should not be
performed simultaneously on the offset registers.
Programmable Flag (PAE, PAF) Operation
Whether the flag offset registers are programmed as
described in
Table 1
or the default values are used, the
programmable almost-empty flag (PAE) and programmable
almost-full flag (PAF) states are determined by their corre-
sponding offset registers and the difference between the read
and write pointers.
Table 1. Writing the Offset Registers
LD
0
WEN
0
WCLK
[1]
Selection
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
No Operation
Write Into FIFO
No Operation
and is set LOW when the number of unread words in the FIFO
is greater than or equal to CY7C4281 (64K-m) and CY7C4291
(128K-m). PAF is set HIGH by the LOW-to-HIGH transition of
WCLK when the number of available memory locations is
greater than m.
Table 2. Status Flags
Number of Words in FIFO
CY7C4281
0
1 to n
[2]
0
1 to n
[2]
CY7C4291
FF PAF PAE EF
H
H
H
H
H
L
L
L
L
H
H
H
L
H
H
H
H
(n+1) to (65536
−(m+1))
(n+1) to (131072−(m+1))
H
(65536
−
m)
[3]
to 65535 131072
−
m)
[3]
to 131071
H
65536
131072
L
Width Expansion Configuration
Word width may be increased simply by connecting the corre-
sponding input controls signals of multiple devices. A
composite flag should be created for each of the end-point
status flags (EF and FF). The partial status flags (PAE and
PAF) can be detected from any one device.
Figure 2
demon-
strates a 18-bit word width by using two CY7C42X1s. Any
word width can be attained by adding additional CY7C42X1s.
When the CY7C42X1 is in a Width Expansion Configuration,
the Read Enable (REN2) control input can be grounded (see
Figure 2).
In this configuration, the Write Enable 2/Load
(WEN2/LD) pin is set to LOW at Reset so that the pin operates
as a control to load and read the programmable flag offsets.
0
1
1
1
0
1
Flag Operation
The CY7C4281/91 devices provide five flag pins to indicate
the condition of the FIFO contents. Empty, Full, PAE, and PAF
are synchronous.
Full Flag
The Full Flag (FF) will go LOW when the device is full. Write
operations are inhibited whenever FF is LOW regardless of the
state of WEN1 and WEN2/LD. FF is synchronized to WCLK,
i.e., it is exclusively updated by each rising edge of WCLK.
Empty Flag
The Empty Flag (EF) will go LOW when the device is empty.
Read operations are inhibited whenever EF is LOW,
regardless of the state of REN1 and REN2. EF is synchronized
to RCLK, i.e., it is exclusively updated by each rising edge of
RCLK.
The number formed by the empty offset least significant bit
register and empty offset most significant bit register is
referred to as n and determines the operation of PAE. PAF is
synchronized to the LOW-to-HIGH transition of RCLK by one
flip-flop and is LOW when the FIFO contains n or fewer unread
words. PAE is set HIGH by the LOW-to-HIGH transition of
RCLK when the FIFO contains (n + 1) or greater unread words.
The number formed by the full offset least significant bit
register and full offset most significant bit register is referred to
as m and determines the operation of PAF. PAE is synchro-
nized to the LOW-to-HIGH transition of WCLK by one flip-flop
Note:
1. The same selection sequence applies to reading from the registers. REN1 and REN2 are enabled and a read is performed on the LOW-to-HIGH transition of RCLK.
2. n = Empty Offset (n = 7 default value).
3. m = Full Offset (m = 7 default value).
Document #: 38-06007 Rev. *C
Page 4 of 16
CY7C4281
CY7C4291
RESET (RS)
DATA IN (D)
18
9
9
RESET (RS)
READ CLOCK (RCLK)
READ ENABLE 1 (REN1)
OUTPUT ENABLE (OE)
PROGRAMMABLE(PAE)
EMPTY FLAG (EF) #1
EMPTY FLAG (EF) #2
WRITECLOCK (WCLK)
WRITE ENABLE 1(WEN1)
WRITE ENABLE 2/LOAD
(WEN2/LD)
PROGRAMMABLE(PAF)
FULL FLAG (FF) # 1
FULL FLAG (FF) # 2
CY7C4281/91
CY7C4281/91
FF
EF
9
FF
EF
9
DATA OUT (Q)
18
Read Enable 2 (REN2)
Read Enable 2 (REN2)
Figure 2. Block Diagram of 64k x 9/128k x 9 Deep Sync FIFO Memory Used in a Width Expansion Configuration
///////////////24MHZ时钟设置//////////////////////////////////////////////////////////////
UCSCTL3 |=SELREF__REFOCLK;
__bis_SR_register(SCG0); //disable the FLL control ......
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