D ts e t
aa h e
R c e t r lc r nc
o h se Ee to is
Ma u a t r dCo o e t
n fc u e
mp n n s
R c e tr b a d d c mp n ns ae
o h se rn e
o oet r
ma ua trd u ig ete dewaes
n fcue sn i r i/ fr
h
p rh s d f m te oiia s p l r
uc a e r
o h r n l u pi s
g
e
o R c e tr waes rce td f m
r o h se
fr e rae r
o
te oiia I. Al rce t n ae
h
r nl P
g
l e rai s r
o
d n wi tea p o a o teOC
o e t h p rv l f h
h
M.
P r aetse u igoiia fcoy
at r e td sn r n la tr
s
g
ts p o rmso R c e tr e eo e
e t rga
r o h se d v lp d
ts s lt n t g aa te p o u t
e t oui s o u rne
o
rd c
me t o e c e teOC d t s e t
es r x e d h
M aa h e.
Qu l yOv riw
ai
t
e ve
• IO- 0 1
S 90
•A 92 cr ct n
S 1 0 et ai
i
o
• Qu l e Ma ua trr Ls (
ai d
n fcues it QML MI- R -
) LP F
385
53
•C a sQ Mitr
ls
lay
i
•C a sVS a eL v l
ls
p c ee
• Qu l e S p l r Ls o D sr uos( L )
ai d u pi s it f it b tr QS D
e
i
•R c e trsacic l u pir oD A a d
o h se i
r ia s p l t L n
t
e
me t aln u t a dD A sa d r s
es lid sr n L tn ad .
y
R c e tr lcrnc , L i c mmi e t
o h se Ee t is L C s o
o
tdo
t
s p ligp o u t ta s t f c so r x e t-
u pyn rd cs h t ai y u tme e p ca
s
t n fr u lya daee u loto eoiial
i s o q ai n r q a t h s r n l
o
t
g
y
s p l db id sr ma ua trr.
u pi
e yn ut
y n fcues
T eoiia ma ua trr d ts e t c o a yn ti d c me t e e t tep r r n e
h r n l n fcue’ aa h e a c mp n ig hs o u n r cs h ef ma c
g
s
o
a ds e ic t n o teR c e tr n fcue v rino ti d vc . o h se Ee t n
n p c ai s f h o h se ma ua trd eso f hs e ie R c e tr lcr -
o
o
isg aa te tep r r n eo i s mio d co p o u t t teoiia OE s e ic -
c u rne s h ef ma c ft e c n u tr rd cs o h r n l M p c a
o
s
g
t n .T pc lv le aefr eee c p r o e o l. eti mii m o ma i m rt g
i s ‘y ia’ au s r o rfrn e up s s ny C r n nmu
o
a
r xmu ai s
n
ma b b s do p o u t h rceiain d sg , i lt n o s mpetsig
y e a e n rd c c aa tr t , e in smuai , r a l e t .
z o
o
n
© 2 1 R cetr l t n s LC Al i t R sre 0 1 2 1
0 3 ohs E cr i , L . lRg s eevd 7 1 0 3
e e oc
h
T l r m r, l s v iw wrcl . m
o e n oe p ae it w . e c o
a
e
s
o ec
TMS470R1VF689, TMS470R1VF688
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS001I – FEBRUARY 2002 – REVISED AUGUST 2005
High-Performance Static CMOS Technology
TMS470R1x 16/32-Bit RISC Core (ARM7TDMI™)
– 24-MHz System Clock (48-MHz Pipeline
Mode)
– Independent 16/32-Bit Instruction Set
– Open Architecture With Third-Party Support
– Built-In Debug Module
Integrated Memory (VF689 only)
– 384K-Byte Program Flash
– Three Banks With 18 Contiguous Sectors
– 16K-Byte Static RAM (SRAM)
Integrated Memory (VF688 only)
– 256K-Byte Program Flash
– Two Banks With 14 Contiguous Sectors
– 12K-Byte Static RAM (SRAM)
Operating Features
– Core Supply Voltage (V
CC
): 1.71 V - 2.05 V
– I/O Supply Voltage (V
CCIO
): 3.0 V - 3.6 V
– Low-Power Modes: STANDBY and HALT
– Industrial/Automotive Temperature Ranges
470+ System Module
– 32-Bit Address Space Decoding
– Bus Supervision for Memory and
Peripherals
– Analog Watchdog (AWD) Timer
– Enhanced Real-Time Interrupt (RTI)
– System Integrity and Failure Detection
Direct Memory Access (DMA) Controller
– 32 Control Packets and 16 Channels
Zero-Pin Phase-Locked Loop (ZPLL)-Based
Clock Module With Prescaler
– Multiply-by-4 or -8 Internal ZPLL Option
– ZPLL Bypass Mode
Ten Communication Interfaces:
– Two Serial Peripheral Interfaces (SPIs)
– 255 Programmable Baud Rates
– Two Serial Communication Interfaces (SCIs)
– 2
24
Selectable Baud Rates
– Asynchronous/Isosynchronous Modes
– Two Standard CAN Controllers (SCC)
– 16-Mailbox Capacity
– Fully Compliant With CAN Protocol,
Version 2.0B
– Class II Serial Interface (C2SIb)
– Normal 10.4 Kbps and 4X Mode 41.6 Kbps
– Three Inter-Integrated Circuit (I2C) Modules
– Multi-Master and Slave Interfaces
– Up to 400 Kbps (Fast Mode)
– 7- and 10-Bit Address Capability
High-End Timer (HET)
– 12 Programmable I/O Channels:
– 12 High-Resolution Pins
– High-Resolution Share Feature (XOR)
– High-End Timer RAM
– 64-Instruction Capacity
External Clock Prescale (ECP) Module
– Programmable Low-Frequency External
Clock (CLK)
12-Channel 10-Bit Multi-Buffered ADC
(MibADC)
– 32-Word FIFO Buffer
– Single- or Continuous-Conversion Modes
– 1.55
μs
Minimum Sample and Conversion
Time
– Calibration Mode and Self-Test Features
Flexible Interrupt Handling
Expansion Bus Module (EBM) (PGE only)
– Supports 8- and 16-Bit Expansion Bus Mem-
ory Interface Mappings
– 40 I/O Expansion Bus Pins
55 Dedicated General-Purpose I/O (GIO) Pins
and 39 Additional Peripheral I/Os (PGE Suffix))
14 Dedicated GIO Pins and 39 Additional Pe-
ripheral I/Os (PZ Suffix)
Eight External Interrupts
Compatible ROM Device (Planned)
On-Chip Scan-Base Emulation Logic,
IEEE Standard 1149.1
(1)
(JTAG) Test-Access
Port
144-Pin Plastic Low-Profile Quad Flatpack
(PGE Suffix)
100-Pin Plastic Low-Profile Quad Flatpack
(PZ Suffix)
Development System Support Tools Available
– Code Composer Studio™ Integrated
Development Environment (IDE)
– HET Assembler and Simulator
– Real-Time In-Circuit Emulation
– Flash Programming
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Code Composer Studio is a trademark of Texas Instruments.
ARM7TDMI is a trademark of Advanced RISC Machines Limited (ARM).
All trademarks are the property of their respective owners.
1 The test-access port is compatible with the IEEE Standard 1149.1-1990,
IEEE Standard Test-Access Port and Boundary Scan Architecture
specification. Boundary scan is not supported on this device.
PRODUCTION DATA information is current as of publication
date. Products conform to specifications per the Texas
Instruments standard warranty. Production processing does
not necessarily include testing of all parameters.
Copyright
©
2005, Texas Instruments Incorporated
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77251-1443
1
微控制器 MCU
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
