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FN4098.1
HS-1115RH
Application Information
Closed Loop Gain Selection
The HS-1115RH features a novel design which allows the
user to select from three closed loop gains, without any
external components. The result is a more flexible product,
fewer part types in inventory, and more efficient use of board
space.
This “buffer” operates in closed loop gains of -1, +1, or +2, and
gain selection is accomplished via connections to the
±inputs.
Applying the input signal to +IN and floating -IN selects a gain
of +1 (see next section for layout caveats), while grounding -IN
selects a gain of +2. A gain of -1 is obtained by applying the
input signal to -IN with +IN grounded.
The table below summarizes these connections:
GAIN
(A
CL
)
-1
+1
+2
CONNECTIONS
+INPUT (PIN 3)
GND
Input
Input
-INPUT (PIN 2)
Input
NC (Floating)
GND
Another straightforward approach is to add a 620Ω resistor
in series with the positive input. This resistor and the
HS-1115RH input capacitance form a low pass filter which
rolls off the signal bandwidth before gain peaking occurs.
This configuration was employed to obtain the datasheet AC
and transient parameters for a gain of +1.
PC Board Layout
The frequency response of this amplifier depends greatly on
the amount of care taken in designing the PC board.
The
use of low inductance components such as chip resis-
tors and chip capacitors is strongly recommended,
while a solid ground plane is a must!
Attention should be given to decoupling the power supplies.
A large value (10μF) tantalum in parallel with a small value
(0.1μF) chip capacitor works well in most cases.
Terminated microstrip signal lines are recommended at the
input and output of the device. Capacitance directly on the
output must be minimized, or isolated as discussed in the
next section.
For unity gain applications, care must also be taken to
minimize the capacitance to ground seen by the amplifier’s
inverting input. At higher frequencies this capacitance will
tend to short the -INPUT to GND, resulting in a closed loop
gain which increases with frequency. This will cause
excessive high frequency peaking and potentially other
problems as well.
An example of a good high frequency layout is the
Evaluation Board shown in Figure 1.
Unity Gain Considerations
Unity gain selection is accomplished by floating the -Input of
the HS-1115RH. Anything that tends to short the -Input to
GND, such as stray capacitance at high frequencies, will
cause the amplifier gain to increase toward a gain of +2. The
result is excessive high frequency peaking, and possible
instability. Even the minimal amount of capacitance associ-
ated with attaching the -Input lead to the PCB results in
approximately 3dB of gain peaking. At a minimum this
requires due care to ensure the minimum capacitance at the
-Input connection.
Table 1 lists five alternate methods for configuring the
HS-1115RH as a unity gain buffer, and the corresponding
performance. The implementations vary in complexity and
involve performance trade-offs. The easiest approach to
implement is simply shorting the two input pins together, and
applying the input signal to this common node. The amplifier
bandwidth drops from 400MHz to 200MHz, but excellent
gain flatness is the benefit. Another drawback to this
approach is that the amplifier input noise voltage and input
offset voltage terms see a gain of +2, resulting in higher
noise and output offset voltages. Alternately, a 100pF
capacitor between the inputs shorts them only at high
frequencies, which prevents the increased output offset
voltage but delivers less gain flatness.
Driving Capacitive Loads
Capacitive loads, such as an A/D input, or an improperly
terminated transmission line will degrade the amplifier’s
phase margin resulting in frequency response peaking and
possible oscillations. In most cases, the oscillation can be
avoided by placing a resistor (R
S
) in series with the output
prior to the capacitance.
R
S
and C
L
form a low pass network at the output, thus limit-
ing system bandwidth well below the amplifier bandwidth of
225MHz. By decreasing R
S
as C
L
increases the maximum
bandwidth is obtained without sacrificing stability.
TABLE 1. UNITY GAIN PERFORMANCE FOR VARIOUS IMPLEMENTATIONS
APPROACH
Remove Pin 2
+R
S
= 620Ω
+R
S
= 620Ω and Remove Pin 2
Short Pins 2, 3
100pF cap. between pins 2, 3
PEAKING (dB)
2.5
0.6
0
0
0.2
BW (MHz)
400
170
165
200
190
+SR/-SR (V/μs)
1200/850
1125/800
1050/775
875/550
900/550
±0.1dB
GAIN FLATNESS
(MHz)
20
25
65
45
19
FN4098.1
2
HS-1115RH
Evaluation Board
The performance of the HS-1115RH may be evaluated using
the HFA11XX Evaluation Board, slightly modified as follows:
1. Remove the 500Ω feedback resistor (R2), and leave the
connection open.
2. a. For A
V
= +1 evaluation, remove the 500Ω gain setting
resistor (R1), and leave pin 2 floating.
b. For A
V
= +2, replace the 500Ω gain setting resistor with
a 0Ω resistor to GND.
The layout and modified schematic of the board are shown
in Figure 1.
To order evaluation boards, please contact your local sales
office.
∞
(A
V
= +1)
or 0Ω (A
V
= +2)
R1
1
50Ω
IN
10μF
0.1μF
-5V
GND
2
3
4
8
7
6
5
V
H
0.1μF
50Ω
OUT
V
L
GND
10μF
+5V
+IN
OUT V+
V
L
V-
GND
1
V
H
FIGURE 1A. SCHEMATIC
FIGURE 1B. TOP LAYOUT
FIGURE 1C. BOTTOM LAYOUT
FIGURE 1. EVALUATION BOARD SCHEMATIC AND LAYOUT
Burn-In Circuit
HS-1115RH CERDIP
R
1
Irradiation Circuit
HS-1115RH CERDIP
R
1
1
2
D
4
V-
D
2
C
2
3
4
8
D
3
V+
C
1
D
1
V-
C
1
1
2
3
4
+
8
-
+
7
6
5
-
7
6
5
C
1
V+
NOTES:
R
1
= 100Ω,
±5%
(Per Socket)
C
1
= C
2
= 0.01μF (Per Socket) or 0.1μF (Per Row) Minimum
D
1
= D
2
= 1N4002 or Equivalent (Per Board)
D
3
= D
4
= 1N4002 or Equivalent (Per Socket)
V+ = +5.5V
±0.5V
V- = -5.5V
±0.5V
NOTES:
R
1
= 100Ω,
±5%
C
1
= 0.01μF
V+ = +5.0V
±0.5V
V- = -5.0V
±0.5V
FN4098.1
3
HS-1115RH
Die Characteristics
DIE DIMENSIONS:
59 mils x 58.2 mils x 19 mils
±1
mil
1500μm x 1480μm x 483μm
±25.4μm
METALLIZATION:
Type: Metal 1: AICu(2%)/TiW
Thickness: Metal 1: 8k
Å
±0.4k
Å
Type: Metal 2: AICu(2%)
Thickness: Metal 2: 16k
Å
±0.8k
Å
GLASSIVATION:
Type: Nitride
Thickness: 4k
Å
±0.5k
Å
WORST CASE CURRENT DENSITY:
< 2 x 10
5
A/cm
2
TRANSISTOR COUNT:
89
SUBSTRATE POTENTIAL (Powered Up):
Floating
Metallization Mask Layout
HS-1115RH
-IN
V
H
V+
OUT
+IN
V-
V-
V
L
V
L
All Intersil semiconductor products are manufactured, assembled and tested under
ISO9000
quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.
Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reli-
able. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may
result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site
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