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TMS320C6414, TMS320C6415, TMS320C6416
FIXED POINT DIGITAL SIGNAL PROCESSORS
SPRS146J − FEBRUARY 2001 − REVISED NOVEMBER 2003
D
Highest-Performance Fixed-Point Digital
Signal Processors (DSPs)
− 2-, 1.67-, 1.39-ns Instruction Cycle Time
− 500-, 600-, 720-MHz Clock Rate
− Eight 32-Bit Instructions/Cycle
− Twenty-Eight Operations/Cycle
− 4000, 4800, 5760 MIPS
− Fully Software-Compatible With C62x
− C6414/15/16 Devices Pin-Compatible
VelociTI.2 Extensions to VelociTI
Advanced Very-Long-Instruction-Word
(VLIW) TMS320C64x DSP Core
− Eight Highly Independent Functional
Units With VelociTI.2 Extensions:
− Six ALUs (32-/40-Bit), Each Supports
Single 32-Bit, Dual 16-Bit, or Quad
8-Bit Arithmetic per Clock Cycle
− Two Multipliers Support
Four 16 x 16-Bit Multiplies
(32-Bit Results) per Clock Cycle or
Eight 8 x 8-Bit Multiplies
(16-Bit Results) per Clock Cycle
− Non-Aligned Load-Store Architecture
− 64 32-Bit General-Purpose Registers
− Instruction Packing Reduces Code Size
− All Instructions Conditional
Instruction Set Features
− Byte-Addressable (8-/16-/32-/64-Bit Data)
− 8-Bit Overflow Protection
− Bit-Field Extract, Set, Clear
− Normalization, Saturation, Bit-Counting
− VelociTI.2 Increased Orthogonality
Viterbi Decoder Coprocessor (VCP) [C6416]
− Supports Over 500 7.95-Kbps AMR
− Programmable Code Parameters
Turbo Decoder Coprocessor (TCP) [C6416]
− Supports up to Six 2-Mbps 3GPP
(6 Iterations)
− Programmable Turbo Code and
Decoding Parameters
L1/L2 Memory Architecture
− 128K-Bit (16K-Byte) L1P Program Cache
(Direct Mapped)
− 128K-Bit (16K-Byte) L1D Data Cache
(2-Way Set-Associative)
− 8M-Bit (1024K-Byte) L2 Unified Mapped
RAM/Cache (Flexible Allocation)
D
Two External Memory Interfaces (EMIFs)
− One 64-Bit (EMIFA), One 16-Bit (EMIFB)
− Glueless Interface to Asynchronous
Memories (SRAM and EPROM) and
Synchronous Memories (SDRAM,
SBSRAM, ZBT SRAM, and FIFO)
− 1280M-Byte Total Addressable External
Memory Space
Enhanced Direct-Memory-Access (EDMA)
Controller (64 Independent Channels)
Host-Port Interface (HPI)
− User-Configurable Bus Width (32-/16-Bit)
32-Bit/33-MHz, 3.3-V PCI Master/Slave
Interface Conforms to PCI Specification 2.2
[C6415/C6416 ]
− Three PCI Bus Address Registers:
Prefetchable Memory
Non-Prefetchable Memory I/O
− Four-Wire Serial EEPROM Interface
− PCI Interrupt Request Under DSP
Program Control
− DSP Interrupt Via PCI I/O Cycle
Three Multichannel Buffered Serial Ports
− Direct Interface to T1/E1, MVIP, SCSA
Framers
− Up to 256 Channels Each
− ST-Bus-Switching-, AC97-Compatible
− Serial Peripheral Interface (SPI)
Compatible (Motorola)
Three 32-Bit General-Purpose Timers
Universal Test and Operations PHY
Interface for ATM (UTOPIA) [C6415/C6416]
− UTOPIA Level 2 Slave ATM Controller
− 8-Bit Transmit and Receive Operations
up to 50 MHz per Direction
− User-Defined Cell Format up to 64 Bytes
Sixteen General-Purpose I/O (GPIO) Pins
Flexible PLL Clock Generator
IEEE-1149.1 (JTAG
†
)
Boundary-Scan-Compatible
532-Pin Ball Grid Array (BGA) Package
(GLZ Suffix), 0.8-mm Ball Pitch
0.13-µm/6-Level Cu Metal Process (CMOS)
3.3-V I/Os, 1.2-V/1.25-V Internal (500 MHz)
3.3-V I/Os, 1.4-V Internal (600 and 720 MHz)
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
C62x, VelociTI.2, VelociTI, and TMS320C64x are trademarks of Texas Instruments.
Motorola is a trademark of Motorola, Inc.
† IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
This document contains information on products in more than one phase
of development. The status of each device is indicated on the page(s)
specifying its electrical characteristics.
Copyright
2003, Texas Instruments Incorporated
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77251−1443
1
ADVANCE INFORMATION
TMS320C6414, TMS320C6415, TMS320C6416
FIXED POINT DIGITAL SIGNAL PROCESSORS
SPRS146J − FEBRUARY 2001 − REVISED NOVEMBER 2003
Table of Contents
revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
GLZ BGA package (bottom view) . . . . . . . . . . . . . . . . . . . . . . 5
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
device characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
device compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
functional block and CPU (DSP core) diagram . . . . . . . . . . . 9
CPU (DSP core) description . . . . . . . . . . . . . . . . . . . . . . . . . 10
memory map summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
peripheral register descriptions . . . . . . . . . . . . . . . . . . . . . . . 15
EDMA channel synchronization events . . . . . . . . . . . . . . . . 28
interrupt sources and interrupt selector . . . . . . . . . . . . . . . . 30
signal groups description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
device configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
multiplexed pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
debugging considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
terminal functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
documentation support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
clock PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
general-purpose input/output (GPIO) . . . . . . . . . . . . . . . . . . 71
power-down mode logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
power-supply sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . .
power-supply decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IEEE 1149.1 JTAG compatibility statement . . . . . . . . . . . . .
EMIF device speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
72
74
74
75
75
bootmode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
absolute maximum ratings over operating case
temperature range . . . . . . . . . . . . . . . . . . . . . . . . . .
recommended operating conditions . . . . . . . . . . . . . . . .
electrical characteristics over recommended ranges of
supply voltage and operating case temperature .
76
77
77
78
recommended clock and control signal transition
behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
parameter measurement information . . . . . . . . . . . . . . . 79
input and output clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
asynchronous memory timing . . . . . . . . . . . . . . . . . . . . . 85
programmable synchronous interface timing . . . . . . . . 89
synchronous DRAM timing . . . . . . . . . . . . . . . . . . . . . . . . 94
HOLD/HOLDA timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
BUSREQ timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
external interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . 108
host-port interface (HPI) timing . . . . . . . . . . . . . . . . . . . 109
peripheral component interconnect (PCI) timing
[C6415 and C6416 only] . . . . . . . . . . . . . . . . . . . . 114
multichannel buffered serial port (McBSP) timing . . . . 117
UTOPIA slave timing [C6415 and C6416 only] . . . . . . 128
timer timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
general-purpose input/output (GPIO) port timing . . . . 132
JTAG test-port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
ADVANCE INFORMATION
2
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77251−1443
TMS320C6414, TMS320C6415, TMS320C6416
FIXED POINT DIGITAL SIGNAL PROCESSORS
SPRS146J − FEBRUARY 2001 − REVISED NOVEMBER 2003
REVISION HISTORY
This data sheet revision history highlights the technical changes made to the SPRS146I device-specific data
sheet to make it an SPRS146J revision.
Scope:
Applicable updates to the C64x device family, specifically relating to the C6414, C6415, and C6416
devices, have been incorporated. Added C6414, C6415, and C6416 silicon revision 2.0 devices and associated
device-specific information at the advance information (AI) stage of development.
PAGE(S)
NO.
6
ADDITIONS/CHANGES/DELETIONS
Description section:
With performance of up to 5760 million instructions per second (MIPS) at a clock rate of 720 MHz ... paragraph:
Changed the MMACS value
from
“2400”
to
“2880 million MACs per second (MMACS)”
Changed the MMACS value
from
“4800”
to
“5760 MMACS”
Table 1, Characteristics of the C6414, C6415, and C6416 Processors:
Added “0011” under the Device_ID for Silicon Revision 2.0
Updated the “Product Status” row to include PD (for 1.03, 1.1) and AI (for 2.0)
DEVICE CONFIGURATIONS section, peripheral selection (C6415 and C6416 devices) bullet:
Changed sub-bullet “MCBSP2_EN (for C6414 or C6416, see Table 27 footnotes)”
to
“MCBSP2_EN (for C6415 or C6416,
see Table 27 footnotes)”
Table 29, C6414, C6415, and C6416 Device Multiplexed Pins:
Changed the MULTIPLEXED PINS NAME for “HWWIL”
to
“HHWIL”
Device and development-support tool nomenclature section
Table 30, TMS320C6414/C6415/C6416 Device Part Numbers (P/Ns) and Ordering Information:
Added the C6414, C6415, and C6416 DEVICE ORDERABLE P/Ns [Silicon Revision
2.0]:
TMX32C6414EGLZ5E0, TMX32C6414EGLZA5E0, TMX32C6414EGLZ6E3, TMX32C6414EGLZA6E3, and
TMX32C6414EGLZ7E3
TMX32C6415EGLZ5E0, TMX32C6415EGLZA5E0, TMX32C6415EGLZ6E3, TMX32C6415EGLZA6E3, and
TMX32C6415EGLZ7E3
TMX32C6416EGLZ5E0, TMX32C6416EGLZA5E0, TMX32C6416EGLZ6E3, TMX32C6416EGLZA6E3, and
TMX32C6416EGLZ7E3
Figure 4, TMS320C64x DSP Device Nomenclature (Including the C6414, C6415, and C6416 Devices)
Added the C6414, C6415, and C6416 silicon revision 2.0 devices (6414E, 6415E, and 6416E)
7
37
42
64−66
68
Clock PLL section:
Table 31, Compatible CLKIN External Clock Sources:
Added “Spread Spectrum Clock Generator, Part Number: MK1714” manufactured by Integrated Circuit Systems
Clock PLL section:
Table 32, TMS320C64x PLL Multiply Factor Options, Clock Frequency Ranges, and Typical Lock Time
Updated the clock frequency ranges for CLKIN, CPU Clock, CLKOUT4, and CLKOUT6 for all CLKMODE multiply factors
(x1, x6, and x12)
INPUT AND OUTPUT CLOCKS section:
Timing requirements for CLKIN for −5E0 devices table:
Timing requirements for CLKIN for −6E3 devices table:
Timing requirements for CLKIN for −7E3 devices table:
Added parameter No. 5, tJ(CLKIN), Peak-to-Peak jitter, CLKIN
Updated/changed Figure 15, CLKIN Timing, to include jitter parameter #5
70
81
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77251−1443
3
ADVANCE INFORMATION
TMS320C6414, TMS320C6415, TMS320C6416
FIXED POINT DIGITAL SIGNAL PROCESSORS
SPRS146J − FEBRUARY 2001 − REVISED NOVEMBER 2003
PAGE(S)
NO.
83
ADDITIONS/CHANGES/DELETIONS
INPUT AND OUTPUT CLOCKS section:
Timing requirements for ECLKIN for EMIFA and EMIFB table:
Added parameter No. 5, tJ(EKI), Peak-to-Peak jitter, ECLKIN
Added “Minimum ECLKIN cycle times
must
be met, even when ECLKIN is generated by an internal clock source.” to the
“Minimum ECLKIN times are based on internal logic speed ...” footnote
Updated/changed Figure 18, ECLKIN Timing for EMIFA and EMIFB, to include jitter parameter #5
106−107
RESET TIMING section:
switching characteristics over recommended operating conditions during reset table:
Added parameter NO. 16, “td(PCLK−RSTH) Delay time, PCLK active to RESET high” with a MIN value of “32N” ns
Added associated footnote to identify “N” and restraints
Figure 36, Reset Timing
Updated figure to include the PCLK signal and parameter 16
117−118
ADVANCE INFORMATION
MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING section:
switching characteristics over recommended operating conditions for McBSP table:
timing requirements for McBSP table:
Added “Minimum CLKR/X cycle times
must
be met, even when CLKR/X is generated by an internal clock source.” to the
“Minimum CLKR/X cycle times are based on internal logic speed ...” footnotes
4
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