Supertex inc.
Four-Channel, High Speed, ±75V 1.25A
Ultrasound Pulser
Features
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HVCMOS technology for high performance
High density integration ultrasound transmitter
0 to ±75V output voltage
±1.25A source and sink current in pulse mode
±400mA source and sink current in CW mode
Up to 20MHz operating frequency
Matched delay times
1.2V to 5.0V CMOS logic interface
Built-in output drain bleed resistors
HV748
General Description
The Supertex HV748 is a four-channel, monolithic, high voltage,
high speed pulse generator. It is designed for portable medical
ultrasound applications. This high voltage and high speed
integrated circuit can also be used for piezoelectric, capacitive or
MEMS sensing in ultrasonic nondestructive detection and sonar
ranger applications.
The HV748 consists of a controller logic interface circuit, level
translators, MOSFET gate drives and high power P-channel and
N-channel MOSFETs as the output stage for each channel.
The output stages of each channel are designed to provide peak
output currents over ±1.8A for pulsing, when in mode 4, with up
to ±75 volt swings. When in mode 1, all the output stages drop
the peak current to ±400mA for low-voltage CW mode operation
to decrease the power consumption of the IC. The P and N type
of power FETs gate drivers are supplied by two floating 9.0VDC
power supplies reference to V
PP
and V
NN
. This direct coupling
topology of the gate drivers not only eliminates two high voltage
capacitors per channel, but also makes the PCB layout easier.
Application
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Portable medical ultrasound imaging
Piezoelectric transducer drivers
NDT ultrasound transmission
Pulse waveform generator
Typical Application Circuit
C1
+1.8 to 3.3V
+9.0V
C2
C3
+75V
V
PP
-9.0V
C4
VPF
0 to +75V
VPP
RGND
RP1
TXP1
TXN1
RN1
RGND
VNF
C7
VNN
0 to -75V
C6
D1
D2
X1
HV
OUT
1
C5
VLL VDD
OTP
EN
MC0
+1.8 to 3.3V
Logic
MC1
PIN1
EN_PWR
VSUB
SUB
Level
Translator
P-Driver
NIN1
Level
Translator
N-Driver
1 of 4 Channels
GREF
VSS
HV748
V
NN
+9.0V
Doc.# DSFP-HV748
C061209
Supertex inc.
www.supertex.com
HV748
Ordering Information
Part Number
HV748K6-G
Package Option
48-Lead QFN (7x7mm)
Packing
260/Tray
-G indicates package is RoHS compliant (‘Green’)
Absolute Maximum Ratings
Parameter
V
SS
, Power supply reference
V
LL
, Positive logic supply
V
DD
, Positive logic and level translator supply
(V
PP
-V
PF
) Positive floating gate drive supply
(V
NF
- V
NN
) Negative gate floating drive supply
(V
PP
-V
NN
) Differential high voltage supply
V
PP
, High voltage positive supply
V
NN
, High voltage negative supply
OTP, Over Temperature Protection output
All logic input PIN
X
, NIN
X
and EN voltages
(V
SUB
- V
SS
) Substrate to V
SS
voltage difference
(V
PP
–TXP
X
) V
PP
to TXP
X
voltage difference
(V
SUB
- TXP
X
) Substrate to TXP
X
voltage difference
(TXN
X
-V
NN
) TXN
X
to V
NN
voltage difference
Operating temperature
Storage temperature
Thermal resistance,
θ
JA
Thermal resistance,
θ
JC
(junction to thermal pad)
Value
0V
-0.5V to +7.0V
-0.5V to +14V
-0.5V to +14V
-0.5V to +14V
+170V
-0.5V to +85V
+0.5V to –85V
-0.5V to +7.0V
-0.5V to +7.0V
+170V
+170V
+170V
+170V
-40°C to 125°C
-65°C to 150°C
29°C/W
0.5°C/W
Pin Configuration
48
1
48-Lead QFN
(top view)
Package Marking
HV748K6
LLLLLLLLL
YYWW
AAA CCC
L = Lot Number
YY = Year Sealed
WW = Week Sealed
A = Assembler ID
C = Country of Origin
= “Green” Packaging
Package may or may not include the following marks: Si or
48-Lead QFN
Typical Thermal Resistance
Package
48-Lead QFN
θ
ja
18
O
C/W
Absolute Maximum Ratings are those values beyond which damage to the device may
occur. Functional operation under these conditions is not implied. Continuous operation
of the device at the absolute rating level may affect device reliability. All voltages are
referenced to device ground.
Power-Up Sequence
Step
1
2
3
4
5
6
Description
V
SUB
V
LL
with logic signal low
V
DD
(V
PP
-V
PF
) and (V
NF
–V
NN
)
V
PP
and V
NN
Logic control signals
Power-Down Sequence
Step
1
2
3
4
5
6
Description
All logic signals go to low
V
PP
and V
NN
(V
PP
-V
PF
) and (V
NF
–V
NN
)
V
DD
V
LL
V
SUB
Doc.# DSFP-HV748
C061209
2
Supertex inc.
www.supertex.com
HV748
Operating Supply Voltages and Current (4 Channel Active)
Sym
V
LL
V
DD
V
PF
V
NF
V
SUB
V
PP
V
NN
SR
MAX
I
LL
I
DDQ
I
DDEN
I
DDEN
I
DDENCW
I
PPQ
I
PPEN
I
PPENCW
I
NNQ
I
NNEN
I
NNENCW
I
PFQ
I
PFEN
I
PFENCW
I
NFQ
I
NFEN
I
NFENCW
Parameter
Logic voltage reference
Internal voltage supply
Positive gate driver supply
Negative gate drive supply
IC substrate voltage
Positive HV supply
Negative HV supply
Slew rate limit of V
PP
, V
NN
V
LL
Current EN = Low
V
DD
Current EN = Low
V
DD
Current EN = High
V
DD
Current MODE = 4
V
DD
Current MODE = 1
V
PP
Current EN = Low
V
PP
Current MODE = 4
V
PP
Current MODE = 1
V
NN
Current EN = Low
V
NN
Current MODE = 4
V
NN
Current MODE = 1
V
PF
Current EN = Low
V
PF
Current MODE = 4
V
PF
Current MODE = 1
V
NF
Current EN = Low
V
NF
Current MODE = 4
V
NF
Current MODE = 1
Min
1.2
8.0
(V
PP
-12)
V
DD
0
-75
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Typ
1.8 to 3.3
9.0
(V
PP
-9.0)
V
PP
-
-
-
35
15
0.75
0.75
2.0
10
250
170
15
250
170
10
50
12
20
25
12
Max
5.0
12
(V
PP
-8.0)
+75
+75
0
25
120
-
2.0
-
-
25
-
-
30
-
-
25
-
-
30
-
-
V
V
V
V
V
V
V
V/μs
μA
μA
mA
mA
mA
μA
mA
mA
μA
mA
mA
μA
mA
mA
μA
mA
mA
---
---
Floating driver voltage supplies.
Must be the most positive potential of
the IC.
---
---
Built-in slew rate detection protection.
---
---
f = 0MHz
f = 5.0MHz, continuous, no loads
f = 0MHz
f = 5.0MHz, continuous, no loads
f = 0MHz
f = 5.0MHz, continuous, no loads
f = 0MHz
f = 5.0MHz, continuous, no loads
f = 0MHz
f = 5.0MHz, continuous, no loads
(Operating conditions, unless otherwise specified, V
SS
= 0V, V
LL
= +3.3V, V
DD
= +9.0V, V
PP
-V
PF
= +9.0V, V
NN
-V
NF
= -9.0V, V
PP
=+75V, V
NN
= -75V, T
A
= 25°C)
Units Conditions
(V
NN
+8.0) (V
NN
+9.0) (V
NN
+12.0)
Note:
All supply current values are for reference only.
Under Voltage and Over Temperature Protection
Sym
V
PULL_UP
V
UVDD
V
UVLL
V
UVVF
V
OL_OTP
I
OTP
T
OTP
T
HYS
Parameter
Open drain pull-up voltage
V
DD
threshold
V
LL
threshold
V
PF
, V
NF
threshold
OTP flag output low voltage
Max. open drain output
current
Over-temperature threshold
OTP output reset hysteresis
Min
-
3.5
0.7
3.5
-
-
95
-
Typ
-
-
-
-
-
1.0
110
7.0
Max
5.0
6.5
1.0
6.5
1.0
-
125
-
Units Conditions
V
V
V
V
V
mA
°C
---
---
---
---
V
LL
= 3.3V, OTP = Active,
I
PULL_UP
= 1.0mA.
---
If over-temperature occurred, OTP
low and all TX outputs will be HiZ.
Doc.# DSFP-HV748
C061209
3
Supertex inc.
www.supertex.com
HV748
DC Electrical Characteristics
Sym
I
OUT
R
ON
C
OSS
Parameter
Output saturation current
Channel resistance
Output capacitance
(Operating conditions, unless otherwise specified, V
SS
= 0V, V
LL
= +3.3V, V
DD
= +9V, V
PF
= V
PP
-9V, V
NF
= V
NN
+ 9V, V
PP
= +75V, V
NN
= -75V, T
A
= 25°C)
Output P-Channel MOSFET, TXP (Mode 4)
Min
1.25
-
-
Typ
1.8
8.0
100*
Max
-
-
-
Units Conditions
A
Ω
pF
---
I
SD
= 100mA
V
DS
= 25V, f = 1.0MHz
Output N-Channel MOSFET, TXN (Mode 4)
Sym
I
OUT
R
ON
C
OSS
Parameter
Output saturation current
Channel resistance
Output capacitance
Min
1.25
-
-
Typ
1.8
7.5
40*
Max
-
-
-
Units Conditions
A
Ω
pF
---
I
SD
= 100mA
V
DS
= 25V, f = 1.0MHz
MOSFET Drain Bleed Resistor
Sym
R
P/N1~4
P
RO
Parameter
Output bleed resistance
Bleed resistors power limit
Min
10
-
Typ
15
-
Max
30
40
Units Conditions
kΩ
mW
---
---
Logic Inputs
Sym
V
IH
V
IL
I
IH
I
IL
C
IN
Parameter
Input logic high voltage
Input logic low voltage
Input logic high current
Input logic low current
Input logic capacitance
Min
(V
LL
-0.4)
0
-
-10
-
Typ
-
-
-
-
-
Max
V
LL
0.4
10
-
5.0*
Units Conditions
V
V
μA
μA
pF
---
---
---
---
---
AC Electrical Characteristics
Sym
t
r
t
f
f
OUT
HD2
t
EN
t
DIS
t
dr
t
df
Δt
DELAY
t
dm
t
j
Parameter
Output rise time
Output fall time
Output frequency range
Second harmonic distortion
Enable time
Disable time
Delay time on inputs rise
Delay time on inputs fall
Delay time matching
Delay on mode change
Delay jitter on rise or fall
(Operating conditions, unless otherwise specified, V
SS
=0V, V
LL
= +3.3V, V
DD
= +9V, V
PF
= (V
PP
- 9V), V
NF
= (V
NN
+9V), V
PP
= +75V, V
NN
= -75V, T
A
= 25°C)
Min
-
-
-
-
-
-
-
-
-
-
-
Typ
35
43
-
-40*
180
2.8
18
18
±2.0
2.5
15*
Max
-
-
20
-
500
10
-
-
-
10
-
Units Conditions
ns
ns
MHz
dB
μs
μs
ns
ns
ns
μs
ps
3.9Ω resistor load
(see timing diagram)
P to N, channel to channel
100Ω resistor load
V
PP
/V
NN
= ±25V, input t
r
50% to HV
OUT
t
r
or t
f
50%, with 330pF//2.5kΩ load
100Ω resistor load
330pF//2.5kΩ load
* Guaranteed by design.
Doc.# DSFP-HV748
C061209
4
Supertex inc.
www.supertex.com
HV748
Switch AC Test Timing Diagram
NINx
PINx
90%
V
PP
t
f
0
t
r
10%
Output
10%
V
NN
90%
V
LL
V
DD
V
SUB
V
PF
V
PP
OTP
EN
MC0
MC1
PIN1
SUB
EN_PWR
Level
Translator
RGND
R
P1
TXP1
TXN1
P-Driver
NIN1
Level
Translator
N-Driver
R
N1
R2
RGND
R1
1of n Channels
G
REF
V
SS
V
NF
V
NN
PINx
t
drp
50%
t
dfp
I
OUT
50%
NINx
50%
t
drn
t
dfn
TXPx
0A
TXNx 0A
50%
I
OUT
Doc.# DSFP-HV748
C061209
5
Supertex inc.
www.supertex.com
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