FINAL
Am486
®
DE2
8-Kbyte Write-Through Embedded Microprocessor
DISTINCTIVE CHARACTERISTICS
s
High-Performance Design
— 66-MHz operating frequency
— Frequent instructions execute in one clock
— 105.6-million bytes/second burst bus at 33 MHz
— Flexible write-through address control
— Dynamic bus sizing for 8-, 16-, and 32-bit buses
— Soft reset capability
s
High On-Chip Integration
— 8-Kbyte unified code and data cache
— Floating-point unit
— Paged, virtual memory management
s
Enhanced System and Power Management
— Stop clock control for reduced power
consumption
— Industry-standard, two-pin System Management
Interrupt (SMI) for power management indepen-
dent of processor operating mode and operating
system
— Static design with Auto Halt Power-Down support
— Wide range of chipsets supporting SMM avail-
able to allow product differentiation
s
Complete 32-Bit Architecture
— Address and data buses
— All registers
— 8-, 16-, and 32-bit data types
s
Standard Features
— 3-V core with 5-V-tolerant I/O
— Binary compatible with all Am486
®
DX
and Am486DX2 microprocessors
— Wide range of support available through the
AMD
®
FusionE86
SM
Program
s
IEEE 1149.1 JTAG Boundary-Scan Compatibility
s
Supports Environmental Protection Agency's
Energy Star program
— 3-V operation reduces power consumption up to
40%
— Energy management capability provides an ex-
cellent base for energy-efficient design
— Works with a variety of energy-efficient, power-
managed devices
s
208-Lead SQFP or 168-Pin PGA Package
GENERAL DESCRIPTION
The Am486DE2 microprocessor is an addition to the
AMD Am486 microprocessor family. The Am486DE2
enhances system performance by incorporating flexible
clock control and enhanced SMM.
The Am486DE2 CPU clock control feature permits the
CPU to be stopped under controlled conditions, allowing
reduced power consumption during system inactivity.
The SMM function is implemented with an industry-stan-
dard, two-pin interface.
Publication ID
20037
Revision
A
Amendment
/0
Issue Date
April 1996
BLOCK DIAGRAM
Power
Plane
Clock
Interface
32-Bit Data Bus
32-Bit Data Bus
32-Bit Linear Address
PCD, PWT
VOLDET
V
CC
, V
SS
Clock
Generator
CLK
STPCLK
Bus Interface
Cache Unit
32
Address
Drivers
Write
Buffers
4x32
Copyback
Buffers
4x32
Writeback
Buffers
4x32
Barrel
Shifter
Register
File
ALU
24
Segmentation
Unit
Descriptor
Registers
Limit and
Attribute
PLA
Paging Unit
24
Translation
Lookaside
Buffer
2
A31–A2
BE3–BE0
Physical
Address
Physical
Address
8-Kbyte
Cache
128
Displacement Bus
Micro-instruction
Prefetcher
32
Code
32-Byte
Stream
Code Queue
32
Data Bus
Transceivers
D31–D0
ADS, W/R, D/C, M/IO,
PCD, PWT, RDY, LOCK,
PLOCK, BOFF, A20M,
BREQ, HOLD, HLDA,
RESET, INTR, NMI,
FERR, UP, IGNNE, SMI,
SMIACT, SRESET
BRDY, BLAST
BS16, BS8
Floating-
Point
Unit
Floating-
Point
Register
File
Central and
Protection
Test Unit
Decoded
Instruction
Path
2x16 Bytes
Instruction
Decode
24
Bus Control
Request
Sequencer
Control
ROM
Burst Bus
Control
Bus Size
Control
Cache
Control
KEN, FLUSH,
AHOLD, CACHE,
EADS, INV,
WB/WT, HITM
Parity
Generation
and Control
JTAG
PCHK,
DP3–DP0
TDI, TCK,
TDO, TMS
2
Am486DE2 Microprocessor
ORDERING INFORMATION
Standard Product
AMD standard products are available in several packages and operating ranges. Valid order numbers are formed by
a combination of the elements below.
Am486 DE2 –66 V
8
T
H C
TEMPERATURE RANGE
C = Commercial
PACKAGE TYPE
H = 208-Lead SQFP
G= 168-Pin PGA
CACHE TYPE
T = Write-through
CACHE SIZE
8 = 8 Kbyte
VOLTAGE
V = V
CC
is 3 V with 5-V tolerance
SPEED OPTION
–66 = 66 MHz
VERSION
DE2 = Clock-doubled with FPU
DEVICE NUMBER/DESCRIPTION
Am486 high-performance CPU
Valid Combinations
Valid Combination
Am486DE2-66V8THC
Am486DE2-66V8TGC
Comment
SQFP package
PGA package
Valid combinations list configurations
planned to be supported in volume for
this device. Consult the local AMD sales
office to confirm availability of specific
valid combinations and to check on
newly released combinations.
Am486DE2 Microprocessor
3
Table of Contents
Distinctive Characteristics ............................................................................................................................ 1
General Description...................................................................................................................................... 1
Block Diagram .............................................................................................................................................. 2
Ordering Information .................................................................................................................................... 3
Connection Diagrams and Pin Designations................................................................................................ 7
168-Pin Grid Array (PGA) Package ....................................................................................................... 7
168-Pin PGA Designations (Functional Grouping) ................................................................................ 8
208-Lead Shrink Quad Flat Pack (SQFP) Package............................................................................... 9
208-Lead SQFP Designations (Functional Grouping) ......................................................................... 10
Logic Symbol.............................................................................................................................................. 11
Pin Descriptions ......................................................................................................................................... 12
A20M.................................................................................................................................................... 12
A31–A2 ................................................................................................................................................ 12
ADS...................................................................................................................................................... 12
AHOLD (Modified)................................................................................................................................ 12
BE3–BE0 ............................................................................................................................................. 12
BLAST (Modified)................................................................................................................................. 12
BOFF ................................................................................................................................................... 12
BRDY ................................................................................................................................................... 12
BREQ................................................................................................................................................... 13
BS8/BS16 ............................................................................................................................................ 13
CACHE (New)...................................................................................................................................... 13
CLK (Modified) ..................................................................................................................................... 13
D31–D0................................................................................................................................................ 13
D/C....................................................................................................................................................... 13
DP3–DP0 ............................................................................................................................................. 13
EADS (Modified) .................................................................................................................................. 13
FERR ................................................................................................................................................... 14
FLUSH (Modified) ................................................................................................................................ 14
HITM (New).......................................................................................................................................... 14
HLDA ................................................................................................................................................... 14
HOLD ................................................................................................................................................... 14
IGNNE.................................................................................................................................................. 14
INTR..................................................................................................................................................... 14
INV (New) ............................................................................................................................................ 14
KEN...................................................................................................................................................... 14
LOCK ................................................................................................................................................... 14
M/IO ..................................................................................................................................................... 15
NMI ...................................................................................................................................................... 15
PCD ..................................................................................................................................................... 15
PCHK ................................................................................................................................................... 15
PLOCK (Modified)................................................................................................................................ 15
PWT ..................................................................................................................................................... 15
RDY ..................................................................................................................................................... 15
RESET ................................................................................................................................................. 15
SMI (New) ............................................................................................................................................ 15
SMIACT (New)..................................................................................................................................... 16
SRESET (New) .................................................................................................................................... 16
STPCLK (New) .................................................................................................................................... 16
TCK...................................................................................................................................................... 16
TDI ....................................................................................................................................................... 16
TDO ..................................................................................................................................................... 16
TMS ..................................................................................................................................................... 16
UP ........................................................................................................................................................ 16
VOLDET (New, 168-Pin PGA Package only) ...................................................................................... 16
4
Am486DE2 Microprocessor
WB/WT (New) ...................................................................................................................................... 16
W/R ...................................................................................................................................................... 16
Functional Description................................................................................................................................ 17
Overview .............................................................................................................................................. 17
Memory ................................................................................................................................................ 17
Modes of Operation ............................................................................................................................. 17
Write-Through Cache Architecture ...................................................................................................... 17
Cache Replacement Description ......................................................................................................... 17
Memory Configuration ......................................................................................................................... 17
Clock Control.............................................................................................................................................. 18
Clock Generation ................................................................................................................................. 18
Stop Clock ........................................................................................................................................... 18
Stop Grant Bus Cycle .......................................................................................................................... 19
Pin State During Stop Grant ................................................................................................................ 19
Clock Control State Diagram ............................................................................................................... 20
SRESET Function ...................................................................................................................................... 20
System Management Mode ....................................................................................................................... 22
Overview .............................................................................................................................................. 22
Terminology ......................................................................................................................................... 22
System Management Interrupt Processing.......................................................................................... 22
Entering System Management Mode .................................................................................................. 26
Exiting System Management Mode ..................................................................................................... 27
Processor Environment ....................................................................................................................... 27
Executing System Management Mode Handler .................................................................................. 28
SMM System Design Considerations .................................................................................................. 31
SMM Software Considerations ............................................................................................................ 34
Test Registers 4 and 5 Modifications ......................................................................................................... 36
TR4 Definition ...................................................................................................................................... 36
TR5 Definition ...................................................................................................................................... 36
Am486DE2 Microprocessor Functional Differences................................................................................... 37
Am486DE2 Microprocessor Identification .................................................................................................. 37
DX Register at RESET ........................................................................................................................ 37
CPUID Instruction ................................................................................................................................ 37
Electrical Data ............................................................................................................................................ 39
Power Connections.............................................................................................................................. 39
Power Decoupling Recommendations................................................................................................. 39
Other Connection Recommendations.................................................................................................. 39
Absolute Maximum Ratings........................................................................................................................ 40
Operating Ranges ...................................................................................................................................... 40
DC Characteristics over Commercial Operating Ranges ........................................................................... 40
Switching Characteristics over Commercial Operating Ranges................................................................. 41
Switching Characteristics for 33-MHz Bus (66-MHz Microprocessor) ................................................. 42
Switching Waveforms .......................................................................................................................... 43
Package Thermal Specifications ................................................................................................................ 48
Physical Dimensions .................................................................................................................................. 50
168-Pin PGA ........................................................................................................................................ 50
208-Lead SQFP ................................................................................................................................... 51
Am486DE2 Microprocessor
5
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