November 2007
H Y B1 8T 5 1 2400B F
H Y B1 8T 5 1 2800B F
H Y B1 8T 5 1 2160B F
512-Mbit Double-Data-Rate-Two SDRAM
DDR2 SDRAM
RoHS Compliant Products
Internet Data Sheet
Rev. 1.2
Internet Data Sheet
HYB18T512[40/80/16]0BF
512-Mbit Double-Data-Rate-Two SDRAM
Revision History: Rev. 1.2, 2007-11
All
Adapted Internet Edition
Changed figures in chapter 7 and chapter 8
Previous Revision:Rev. 1.10, 2007-05
Added more Product types
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qag_techdoc_rev411 / 3.31 QAG / 2007-01-22
03292006-YBYM-WG0Z
2
Internet Data Sheet
HYB18T512[40/80/16]0BF
512-Mbit Double-Data-Rate-Two SDRAM
1
Overview
This chapter gives an overview of the 512-Mbit Double-Data-Rate-Two SDRAM product family and describes its main
characteristics.
1.1
Features
The 512-Mbit Double-Data-Rate-Two SDRAM offers the following key features:
• Off-Chip-Driver impedance adjustment (OCD) and
• 1.8 V
±
0.1 V Power Supply
1.8 V
±
0.1 V (SSTL_18) compatible I/O
On-Die-Termination (ODT) for better signal quality
• DRAM organizations with 4,8,16 data in/outputs
• Auto-Precharge operation for read and write bursts
• Double Data Rate architecture: two data transfers per
• Auto-Refresh, Self-Refresh and power saving Power-
clock cycle four internal banks for concurrent operation
Down modes
• Programmable CAS Latency: 3, 4, 5 and 6
• Average Refresh Period 7.8
µs
at a
T
CASE
lower
• Programmable Burst Length: 4 and 8
than 85 °C, 3.9
µs
between 85 °C and 95 °C
• Differential clock inputs (CK and CK)
• Programmable self refresh rate via EMRS2 setting
• Programmable partial array refresh via EMRS2 settings
• Bi-directional, differential data strobes (DQS and DQS) are
transmitted / received with data. Edge aligned with read
• DCC enabling via EMRS2 setting
• Full and reduced Strength Data-Output Drivers
data and center-aligned with write data.
• DLL aligns DQ and DQS transitions with clock
• 1KB page size for ×4 and ×8, 2KB page size for ×16
• Packages: PG-TFBGA-60, PG-TFBGA-84
• DQS can be disabled for single-ended data strobe
operation
• RoHS Compliant Products
1)
• Commands entered on each positive clock edge, data and
• All Speed grades faster than DDR2–400 comply with
data mask are referenced to both edges of DQS
DDR2–400 timing specifications when run at a clock rate
• Data masks (DM) for write data
of 200 MHz.
• Posted CAS by programmable additive latency for better
command and data bus efficiency
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Rev. 1.2, 2007-11
03292006-YBYM-WG0Z
3
Internet Data Sheet
HYB18T512[40/80/16]0BF
512-Mbit Double-Data-Rate-Two SDRAM
TABLE 1
Performance Table
QAG Speed Code
DRAM Speed Grade
CAS-RCD-RP latencies
Max.
Clock Frequency
CL3
CL4
CL5
CL6
Min. RAS-CAS-Delay
Min. Row Precharge Time
Min. Row Active Time
Min. Row Cycle Time
DDR2
–25F
–800D
5–5–5
–2.5
–800E
6–6–6
200
266
333
400
15
15
45
60
–3
–667C
4–4–4
200
333
333
–
12
12
45
57
–3S
–667D
5–5–5
200
266
333
–
15
15
45
60
–3.7
–533C
4–4–4
200
266
266
–
15
15
45
60
–5
–400B
3–3–3
200
200
–
–
15
15
40
55
Unit
t
CK
MHz
MHz
MHz
MHz
ns
ns
ns
ns
f
CK3
f
CK4
f
CK5
f
CK6
t
RCD
t
RP
t
RAS
t
RC
200
266
400
–
12.5
12.5
45
57.5
1.2
Description
All of the control and address inputs are synchronized with a
pair of externally supplied differential clocks. Inputs are
latched at the cross point of differential clocks (CK rising and
CK falling). All I/Os are synchronized with a single ended
DQS or differential DQS-DQS pair in a source synchronous
fashion.
A 16 bit address bus for ×4 and ×8 organised components
and a 15 bit address bus for ×16 components is used to
convey row, column and bank address information in a RAS-
CAS multiplexing style.
The DDR2 device operates with a 1.8 V
±
0.1 V power
supply. An Auto-Refresh and Self-Refresh mode is provided
along with various power-saving power-down modes.
The functionality described and the timing specifications
included in this data sheet are for the DLL Enabled mode of
operation.
The DDR2 SDRAM is available in TFBGA package.
The 512-Mbit DDR2 DRAM is a high-speed Double-Data-
Rate-Two CMOS Synchronous DRAM device containing 536,
870, 912 bits and internally configured as a quad-bank
DRAM. The 512-Mbit device is organized as 32 Mbit
×4
I/O
×4
banks or 16 Mbit
×8
I/O
×4
banks or 8 Mbit
×16
I/O
×4
banks
chip.
These synchronous devices achieve high speed transfer
rates starting at 400 Mb/sec/pin for general applications. See
Table 1
for performance figures.
The device is designed to comply with all DDR2 DRAM key
features:
1. Posted CAS with additive latency.
2. Write latency = read latency - 1.
3. Normal and weak strength data-output driver.
4. Off-Chip Driver (OCD) impedance adjustment.
5. On-Die Termination (ODT) function.
Rev. 1.2, 2007-11
03292006-YBYM-WG0Z
4
Internet Data Sheet
HYB18T512[40/80/16]0BF
512-Mbit Double-Data-Rate-Two SDRAM
TABLE 2
Ordering Information for RoHS Compliant Products
Product Type
1)
Org. Speed
CAS-RCD-RP
Latencies
2)3)4)
Clock (MHz) Package
Note
5)
Standard Temperature Range (0 °C - +85 °C)
DDR2-800E( 6-6-6)
HYB18T512800BF-2.5
HYB18T512400BF-2.5
HYB18T512160BF-2.5
DDR2-800D( 5-5-5)
HYB18T512800BF-25F
HYB18T512400BF-25F
HYB18T512160BF-25F
DDR2-667D( 5-5-5)
HYB18T512800BF-3S
HYB18T512400BF-3S
HYB18T512160BF-3S
DDR2-667C( 4-4-4)
HYB18T512800BF-3
HYB18T512400BF-3
HYB18T512160BF-3
DDR2-533C( 4-4-4)
HYB18T512800BF-3.7
HYB18T512400BF-3.7
HYB18T512160BF-3.7
DDR2-400B( 3-3-3)
HYB18T512800BF-5
HYB18T512400BF-5
HYB18T512160BF-5
1)
2)
3)
4)
5)
×8
×4
×16
×8
×4
×16
×8
×4
×16
×8
×4
×16
×8
×4
×16
×8
×4
×16
DDR2-800E
DDR2-800E
DDR2-800E
DDR2-800D
DDR2-800D
DDR2-800D
DDR2-667D
DDR2-667D
DDR2-667D
DDR2-667C
DDR2-667C
DDR2-667C
DDR2-533C
DDR2-533C
DDR2-533C
DDR2-400B
DDR2-400B
DDR2-400B
6-6-6
6-6-6
6-6-6
5-5-5
5-5-5
5-5-5
5-5-5
5-5-5
5-5-5
4-4-4
4-4-4
4-4-4
4-4-4
4-4-4
4-4-4
3-3-3
3-3-3
3-3-3
400
400
400
400
400
400
333
333
333
333
333
333
266
266
266
200
200
200
PG-TFBGA-60
PG-TFBGA-60
PG-TFBGA-84
PG-TFBGA-60
PG-TFBGA-60
PG-TFBGA-84
PG-TFBGA-60
PG-TFBGA-60
PG-TFBGA-84
PG-TFBGA-60
PG-TFBGA-60
PG-TFBGA-84
PG-TFBGA-60
PG-TFBGA-60
PG-TFBGA-84
PG-TFBGA-60
PG-TFBGA-60
PG-TFBGA-84
For detailed information regarding Product Type of Qimonda please see chapter "Product Nomenclature" of this datasheet.
CAS: Column Address Strobe
RCD: Row Column Delay
RP: Row Precharge
RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Rev. 1.2, 2007-11
03292006-YBYM-WG0Z
5
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