HB52E329E1-A6A/B6A
256 MB Registered SDRAM DIMM
32-Mword
×
72-bit, 100 MHz Memory Bus, 1-Bank Module
(9 pcs of 32 M
×
8 Components)
PC100 SDRAM
ADE-203-950 (Z)
Preliminary, Rev.0.0
Sept. 18, 1998
Description
The HB52E329E1 belongs to 8-byte DIMM (Dual In-line Memory Module) family, and have been
developed as an optimized main memory solution for 8-byte processor applications. The HB52E329E1 is a
32M
×
72
×
1-bank Synchronous Dynamic RAM Module, mounted 9 pieces of 256-Mbit SDRAM
(HM5225805A-A6/B6) sealed in TSOP package, 2 pieces of register driver (ALVC162835), a piece of
PLL clock driver (CDC2509A) and 1 piece of serial EEPROM (2-kbit EEPROM) for Presence Detect
(PD). An outline of the HB52E329E1 is 168-pin socket type package (dual lead out). Therefore, the
HB52E329E1 makes high density mounting possible without surface mount technology. The
HB52E329E1 provides common data inputs and outputs. Decoupling capacitors are mounted beside each
TSOP on the module board.
Features
•
Fully compatible with : JEDEC standard outline registered 8-byte DIMM
: Intel PCB Reference design (Rev.1.0)
•
168-pin socket type package (dual lead out)
Outline: 133.37 mm (Length)
×
38.1 mm (Height)
×
4.00 mm (Thickness)
Lead pitch: 1.27 mm
•
3.3 V power supply
•
Clock frequency: 100 MHz (max)
•
LVTTL interface
•
Data bus width:
×
72 ECC
•
Single pulsed
RAS
•
4 Banks can operates simultaneously and independently
•
Burst read/write operation and burst read/single write operation capability
•
Programmable burst length: 1/2/4/8/full page
•
2 variations of burst sequence
Sequential (BL = 1/2/4/8/full page)
Interleave (BL = 1/2/4/8)
HB52E329E1-A6A/B6A
•
Programmable
CE
latency : 3/4 (HB52E329E1-A6A)
: 4 (HB52E329E1-B6A)
•
Byte control by DQMB
•
Refresh cycles: 8192 refresh cycles/64 ms
•
2 variations of refresh
Auto refresh
Self refresh
•
Full page burst length capability
Sequential burst
Burst stop capability
Ordering Information
Type No.
HB52E329E1-A6A
HB52E329E1-B6A
Frequency
100 MHz
100 MHz
CE
latency
3/4
4
Package
Contact pad
168-pin dual lead out socket type Gold
Pin Arrangement
1 pin 10 pin 11 pin
40 pin 41 pin
84 pin
85 pin 94 pin 95 pin 124 pin 125 pin
168 pin
2
HB52E329E1-A6A/B6A
Pin No.
36
37
38
39
40
41
42
Pin name
A6
A8
A10 (AP)
BA1
V
CC
V
CC
CK0
Pin No.
78
79
80
81
82
83
84
Pin name
V
SS
CK2
NC
WP
SDA
SCL
V
CC
Pin No.
120
121
122
123
124
125
126
Pin name
A7
A9
BA0
A11
V
CC
CK1
A12
Pin No.
162
163
164
165
166
167
168
Pin name
V
SS
CK3
NC
SA0
SA1
SA2
V
CC
Pin Description
Pin name
A0 to\~A12
Function
Address input
Row address
A0 to A12
Column address A0 to A9
BA0/BA1
DQ0 to DQ63
CB0 to CB7
S0, S2
RE
CE
W
DQMB0 to DQMB7
CK0 to CK3
CKE0
WP
SDA
REGE*
1
SCL
SA0 to SA2
V
CC
V
SS
NC
Note:
Bank select address
Data input/output
Check bit (Data input/output)
Chip select input
Row enable (RAS) input
Column enable (CAS) input
Write enable input
Byte data mask
Clock input
Clock enable input
Write protect for serial PD
Data input/output for serial PD
Register enable
Clock input for serial PD
Serial address input
Primary positive power supply
Ground
No connection
1. REGE is the Register Enable pin which permits the DIMM to operate in “buffered” mode and
“registered” mode. To conform to this specification, mother boards must pull this pin to high
state (“registered” mode).
BA0/BA1
4
HB52E329E1-A6A/B6A
Serial PD Matrix*
1
Byte No. Function described
0
1
2
3
4
5
6
7
8
9
Number of bytes used by
module manufacturer
Total SPD memory size
Memory type
Number of row addresses bits
Number of column addresses
bits
Number of banks
Module data width
Module data width (continued)
Module interface signal levels
SDRAM cycle time
(highest
CE
latency)
10 ns
SDRAM access from Clock
(highest
CE
latency)
6 ns
Module configuration type
Refresh rate/type
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
0
1
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
1
0
0
1
0
80
08
04
0D
0A
01
48
00
01
A0
128
256 byte
SDRAM
13
10
1
72
0 (+)
LVTTL
CL = 3
10
0
1
1
0
0
0
0
0
60
*
7
11
12
0
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
02
82
ECC
Normal
(7.8125
µs)
Self refresh
32M
×
8
×
8
1 CLK
13
14
15
SDRAM width
Error checking SDRAM width
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
1
08
08
01
SDRAM device attributes:
0
minimum clock delay for back-to-
back random column addresses
SDRAM device attributes:
Burst lengths supported
SDRAM device attributes:
number of banks on SDRAM
device
SDRAM device attributes:
CE
latency
(-A6A)
(-B6A)
1
0
16
17
0
0
0
0
0
0
1
0
1
1
1
0
1
0
8F
04
1, 2, 4, 8,
full page
4
18
0
0
0
0
0
0
1
0
06
2/3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
1
0
0
0
1
0
1
1
0
04
01
01
16
3
0
0
Registered
19
20
21
SDRAM device attributes:
CS
latency
SDRAM device attributes:
W
latency
SDRAM device attributes
5