Output Offset Voltage, Transformer Coupled Across 70 Ohms
Rise/Fall Time
POWER SUPPLY REQUIREMENTS
Voltages/Tolerances (Note 9)
+3.3 V (Logic Power)
+5 V (RAM and Transceiver Power)
Current Drain
BU-65569i1
+5 V
• Idle
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
+3.3 V (Logic)
BU-65569i2
+5 V
• Idle
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
+3.3 V (Logic)
BU-65569i3
+5 V
• Idle
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
+3.3 V (Logic)
BU-65569i4
+5 V
• Idle
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
+3.3 V (Logic)
POWER DISSIPATION
BU-65569i1
• Idle
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
BU-65569i2
• Idle
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
BU-65569i3
• Idle
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
MIN.
TYP.
MAX.
UNITS
-0.3
-0.3
1.000
0.200
6.0
7.0
V
V
kOhm
VP-P
VPEAK
0.860
10
18
-250
100
20
150
150
27
250
300
VP-P
mVPEAK
ns
3.0
4.75
3.3
5.0
3.6
5.5
V
V
100
210
320
540
80
mA
mA
mA
mA
mA
200
420
640
1.08
120
mA
mA
mA
A
mA
300
630
960
1.62
160
mA
mA
mA
A
mA
400
840
1.28
2.16
200
mA
mA
A
A
mA
0.84
1.12
1.41
1.98
1.53
2.10
2.67
3.81
2.23
3.08
3.93
5.64
W
W
W
W
W
W
W
W
W
W
W
W
Data Device Corporation
www.ddc-web.com
3
BU-65569i
F-11/05-0
TABLE 1. BU-65569IX SPECIFICATION TABLE (CONT.)
PARAMETER
POWER DISSIPATION (CONT.)
BU-65569i4
• Idle
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
1553 MESSAGE TIMING
Completion of CPU Write (BC Start)-to-Start of
Next Message (Non-Enhanced BC Mode)
BC Intermessage Gap - (Note 5)
Non-Enhanced (Mini-ACE Compatible) BC Mode
Enhanced BC Mode (Note 6)
BC/RT/MT Response Timeout (Note 7)
18.5 Nominal
22.5 Nominal
50.5 Nominal
128.0 Nominal
RT Response Time (Mid-Parity to Mid-Sync) (Note 8)
Transmitter Watchdog Timeout
THERMAL
Ambient Operating Temperature Range (BU-65569iX-200)
Ambient Operating Temperature Range (BU-65569iX-300)
Storage Temperature Range
PHYSICAL CHARACTERISTICS
Size
2.5
MIN.
TYP.
MAX.
UNITS
2.92
4.06
5.20
7.47
W
W
W
W
µs
µs
µs
9.5
10.0 to 10.5
17.5
21.5
49.5
127
4
18.5
22.5
50.5
129.5
660.5
-40
0
-40
6.875(L) X 4.200(H)
(172.72 X 106.68)
5.50
(156)
+85
+55
+85
19.5
23.5
51.5
131
7
µs
µs
µs
µs
µs
µs
°C
°C
°C
in
(mm)
oz
(g)
Weight (4 channel card)
Notes:
(Notes 1 through 3 are applicable to the Input Impedance specification.)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
The specifications are applicable for both unpowered and powered conditions.
The specifications assume a 2-volt rms balanced, differential, sinusoidal input. The applicable frequency range is 75 kHz to 1 MHz.
Minimum impedance is guaranteed over the operating range, but is not tested.
Assumes a common-mode voltage within the frequency range of dc to 2 MHz, applied to pins of the isolation transformer on the stub side (transformer cou-
pled), and referenced to signal.
Typical value for minimum intermessage gap time. Under software control, this may be lengthened to 65,535 µs - message time, in increments of 1 µs. If
ENHANCED CPU ACCESS, bit 14 of Configuration Register #6, is set to logic "1", then host accesses during BC Start-of-Message (SOM) and End-of-
Message (EOM) transfer sequences could have the effect of lengthening the intermessage gap time. For each host access during an SOM or EOM sequence,
the intermessage gap time will be lengthened by 6 clock cycles. Since there are 7 internal transfers during SOM, and 5 during EOM, this could theoretically
lengthen the intermessage gap by up to 72 clock cycles; i.e., up to 7.2 µs with a 10 MHz clock, 6.0 µs with a 12 MHz clock, 4.5 µs with a 16 MHz clock, or 3.6
µs at 20 MHz clock.
For enhanced BC mode, the typical value for intermessage gap time is approximately 10 clock cycles longer than for the non-enhanced BC mode. That is, an
addition of 1.0 µs at 10 MHz, 833 ns at 12 MHz, 625 ns at 16 MHz, or 500 ns at 20 MHz.
Software programmable (4 options). Includes RT-to-RT Timeout (measured mid parity of transmit Command Word to mid-sync of Transmitting RT Status
Word).
Measured from mid-parity crossing of Command Word to mid-sync crossing of RT's Status Word.
The standard BU-65569iX board requires +3.3 volt and +5 volt power. For applications where +3.3 volts is not available, DDC is able to supply a non-standard
version of the BU-65569iX card requiring only +5 volts (consult factory).
Power dissipation specifications assume a transformer coupled configuration with external dissipation (while transmitting) of:
0.14 watts for the active isolation transformer
0.08 watts for the active bus coupling transformer
0.45 watts for each of the two bus isolation resistors and
0.15 watts for each of the two bus termination resistors
Data Device Corporation
www.ddc-web.com
4
BU-65569i
F-011/05-0
INTRODUCTION
The BU-65569iX is a single-channel or multi-channel MIL-STD-
1553 PCI card. The BU-65569iX is available with one to four dual
redundant 1553 channels. The design of the BU-65569iX lever-
ages the BU-61864 Enhanced Mini-ACE. Each channel may be
independently programmed for BC/RT/Monitor, or RT/Monitor
mode.
Advanced architectural features of the Enhanced Mini-ACE
include a highly autonomous bus controller, an RT providing a
wide variety of buffering options, and a selective message mon-
itor. Each Enhanced Mini-ACE channel incorporates 3.3-volt
logic to reduce power consumption and 64K words of RAM.
The BU-65569iX is supported by free software, including a C
library and a Windows® 9x/2000/XP and Windows NT® driver.
The library and driver comprise a suite of C function calls that
serves to offload a great deal of low-level tasks from the appli-
cation programmer. This software supports all of the Enhanced
Mini-ACE's advanced architectural features. Library and driver
support is also available for Linux.
interrupts, for the purpose of performing messaging to the host
processor.
Another important feature for the Enhanced Mini-ACE is the
incorporation of a fully autonomous built-in self-test. This test
provides comprehensive testing of the internal protocol logic. A
separate test verifies the operation of the Enhanced Mini-ACE's
internal RAM. Since the self-tests are fully autonomous, they
eliminate the need for the host to write and read stimulus and
response vectors.
The Enhanced Mini-ACE RT offers the choice of single, double,
and circular buffering for individual subaddresses or a global cir-
cular buffering option for multiple (or all) receive subaddresses,
a 50% rollover interrupt for circular buffers, an interrupt status
queue for logging up to 32 interrupt events, and an option to
automatically initialize to RT mode with the Busy bit set.
PCI INTERFACE
As a means of minimizing power consumption and dissipation,
the design of the standard BU-65569iX board utilizes +3.3 volt
power for the PCI interface and 1553 (Enhanced Mini-ACE)
logic, and +5 volt power for the 1553 transceivers and RAM.
The BU-65569iX's PCI interface is a fully compliant target (slave)
agent, as defined by the PCI Local Bus Specification Revision
2.2, using a 32-bit interface that operates at clock speeds of up
to 33 MHz, in a 3.3 volt or 5 volt signaling environment. The inter-
face supports PCI interrupts and contains a 32 X 32 FIFO to
accelerate burst write transfers from the PCI host. That is, it's
possible to perform a burst write of 32 16-bit words (i.e., all of the
data words of a 1553 message) by means of sixteen 32-bit PCI
transfers in approximately 500 ns.
The BU-65569iX contains only a single set of configuration reg-
isters such that all of the Enhanced Mini-ACE(s) memory and
register space may be addressed through a single PCI function.
Internal registers implement the Subsystem Vendor and Device
ID. There are two Base Address Registers, utilized to implement
the Enhanced Mini-ACE memory space (BAR0) and register
space (BAR1). The Base Address Register mapping is contained
in PCI configuration register space.
The ACE register mapping is located in PCI memory space,
allowing for full PCI access to all 1553 terminals. The BU-
65569iX configuration registers and the Enhanced Mini-ACE
RAM (64K X 16 each) are accessed in 32-bit words, while all
ACE registers are accessed as 16-bit words. If a 32-bit read is
performed from the PCI bus in ACE register space only the first
16 bits of data are valid. ACE memory may also be accessed in
16-bit words, but memory is accessed sequentially, allowing for
32-bits of data to be written to or read from the PCI bus.
ENHANCED MINI-ACE
The BU-65569iX PCI card incorporates a PCI bridge, along with
between one and four of DDC's BU-61864 Enhanced Mini-ACE
hybrids. Each Enhanced Mini-ACE comprises a complete, inde-
pendent interface between the PCI Bridge and a MIL-STD-1553
bus. The Enhanced Mini-ACE hybrids provide software compati-
bility with DDC's older generation ACE and Mini-ACE (Plus) ter-
minals.
The BU-61864 Enhanced Mini-ACE provides complete multipro-
tocol support of MIL-STD-1553A/B/McAir and STANAG 3838.
These hybrids include dual transceivers along with protocol, host
interface, memory management logic; and 64K X 16 of RAM.
There is built-in parity checking for this RAM.
The Enhanced Mini-ACE’s include a 5V, voltage source trans-
ceiver for improved line driving capability, with options for MIL-
STD-1760 compliance (20 V
P-P
minimum transmitter voltage) or
McAir compatibility (consult factory). As a means of reducing
power consumption, the Mini-ACE’s logic is powered by 3.3V.
One of the new salient features of the Enhanced Mini-ACE is its
new bus controller architecture. The Enhanced BC's highly
autonomous message sequence control engine provides a
means for offloading the host processor for implementing multi-
frame message scheduling, message retry and bus switching
schemes, data double buffering, and asynchronous message
insertion. In addition, the Enhanced BC mode includes 8 gener-
al purpose flag bits, a general purpose queue, and user-defined
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