OMC952723096.
Hitachi Single-Chip Microcomputer
H8/3297 Series
H8/3297
HD6473297, HD6433297
H8/3296
HD6433296
H8/3294
HD6473294, HD6433294
H8/3292
HD6433292
Hardware Manual
2nd Edition
When using this document, keep the following in mind:
1. This document may, wholly or partially, be subject to change without notice.
2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole
or part of this document without Hitachi’s permission.
3. Hitachi will not be held responsible for any damage to the user that may result from
accidents or any other reasons during operation of the user’s unit accoording to this
document.
4. Circuitry and other examples described herein are meant merely to indicate the
characteristics and performance of Hitachi’s semiconductor products. Hitachi assumes no
responsibility for any intellectual property claims or other problems that may result from
applications based on the examples described herein.
5. No license is granted by implication or otherwise under any patents or other rights of any
third party or Hitachi, Ltd.
6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL
APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales
company. Such use includes, but is not limited to, use in life support system. Buyers of
Hitachi’s products are requested to notify the relevant hitachi sales offices when planning to
use the products in MEDICAL APPLICATIONS.
Preface
The H8/3297 Series is a series of high-performance microcontrollers with a fast H8/300 CPU core
and a set of on-chip supporting functions optimized for embedded control. These include ROM,
RAM, three types of timers, a serial communication interface, A/D converter, I/O ports, and other
functions needed in control system configurations, so that compact, high-performance systems can
be implemented easily. The series includes the H8/3297 with 60-kbyte ROM and 2-kbyte RAM, the
H8/3296 with 48-kbyte ROM and 2-kbyte RAM, H8/3294 with 32-kbyte ROM and 1-kbyte RAM,
and the H8/3292 with 16-kbyte ROM and 512-byte RAM.
The entire H8/3297 Series is available in mask-ROM versions. The H8/3297 and H8/3294 are also
available in ZTAT™* (zero turn-around time) versions, providing a quick and flexible response to
conditions from ramp-up through full-scale volume production, even for applications with
frequently-changing specifications.
This manual describes the hardware of the H8/3297 Series. Refer to the
H8/300 Series
Programming Manual
for a detailed description of the instruction set.
Note: * ZTAT™ is a registered trademark of Hitachi, Ltd.
Contents
Section 1
1.1
1.2
1.3
Overview
.....................................................................................................
Overview ........................................................................................................................
Block Diagram................................................................................................................
Pin Assignments and Functions......................................................................................
1.3.1
Pin Arrangement.............................................................................................
1.3.2
Pin Functions ..................................................................................................
1
1
5
6
6
9
Section 2
2.1
CPU
............................................................................................................... 17
17
17
18
18
19
19
19
20
21
22
23
24
24
26
30
31
33
34
34
36
40
42
43
45
45
46
46
46
47
47
49
2.2
2.3
2.4
2.5
2.6
2.7
Overview ........................................................................................................................
2.1.1
Features...........................................................................................................
2.1.2
Address Space.................................................................................................
2.1.3
Register Configuration....................................................................................
Register Descriptions......................................................................................................
2.2.1
General Registers............................................................................................
2.2.2
Control Registers ............................................................................................
2.2.3
Initial Register Values ....................................................................................
Data Formats...................................................................................................................
2.3.1
Data Formats in General Registers .................................................................
2.3.2
Memory Data Formats....................................................................................
Addressing Modes ..........................................................................................................
2.4.1
Addressing Mode............................................................................................
2.4.2
Calculation of Effective Address....................................................................
Instruction Set.................................................................................................................
2.5.1
Data Transfer Instructions ..............................................................................
2.5.2
Arithmetic Operations ....................................................................................
2.5.3
Logic Operations ............................................................................................
2.5.4
Shift Operations ..............................................................................................
2.5.5
Bit Manipulations ...........................................................................................
2.5.6
Branching Instructions....................................................................................
2.5.7
System Control Instructions ...........................................................................
2.5.8
Block Data Transfer Instruction .....................................................................
CPU States ......................................................................................................................
2.6.1
Overview.........................................................................................................
2.6.2
Program Execution State ................................................................................
2.6.3
Exception-Handling State...............................................................................
2.6.4
Power-Down State ..........................................................................................
Access Timing and Bus Cycle........................................................................................
2.7.1
Access to On-Chip Memory (RAM and ROM) .............................................
2.7.2
Access to On-Chip Register Field and External Devices ...............................
Section 3
3.1
MCU Operating Modes and Address Space
..................................... 53
53
53
54
54
56
57
3.2
3.3
3.4
Overview ........................................................................................................................
3.1.1
Mode Selection ...............................................................................................
3.1.2
Mode and System Control Registers .............................................................
System Control Register (SYSCR).................................................................................
Mode Control Register (MDCR) ....................................................................................
Address Space Map in Each Operating Mode................................................................
Section 4
4.1
4.2
Exception Handling
.................................................................................. 61
61
61
61
61
64
64
64
66
68
68
69
74
75
76
4.3
4.4
Overview ........................................................................................................................
Reset
........................................................................................................................
4.2.1
Overview.........................................................................................................
4.2.2
Reset Sequence ...............................................................................................
4.2.3
Disabling of Interrupts after Reset..................................................................
Interrupts ........................................................................................................................
4.3.1
Overview.........................................................................................................
4.3.2
Interrupt-Related Registers.............................................................................
4.3.3
External Interrupts ..........................................................................................
4.3.4
Internal Interrupts ...........................................................................................
4.3.5
Interrupt Handling ..........................................................................................
4.3.6
Interrupt Response Time.................................................................................
4.3.7
Precaution .......................................................................................................
Note on Stack Handling..................................................................................................
Section 5
5.1
Wait-State Controller
............................................................................... 77
77
77
77
78
78
78
78
80
5.2
5.3
Overview ........................................................................................................................
5.1.1
Features...........................................................................................................
5.1.2
Block Diagram................................................................................................
5.1.3
Input/Output Pins............................................................................................
5.1.4
Register Configuration....................................................................................
Register Description .......................................................................................................
5.2.1
Wait-State Control Register (WSCR).............................................................
Wait Modes.....................................................................................................................
Section 6
6.1
Clock Pulse Generator
............................................................................. 83
83
83
84
85
90
90
6.2
6.3
6.4
Overview ........................................................................................................................
6.1.1
Block Diagram................................................................................................
6.1.2
Wait-State Control Register (WSCR).............................................................
Oscillator Circuit ............................................................................................................
Duty Adjustment Circuit.................................................................................................
Prescaler ........................................................................................................................
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