CD/74HC4051, CD54/74HCT4051, CD54/74HC4052,
www.ti.com
SCHS122J
–
NOVEMBER 1997
–
REVISED FEBRUARY 2011
CD74HCT4052, CD54/74HC4053, CD54/74HC54053
HIGH-SPEED CMOS LOGIC ANALOG MULTIPLEXERS/DEMULTIPLEXERS
Check for Samples:
CD/74HC4051, CD54/74HCT4051, CD54/74HC4052,
1
FEATURES
•
•
•
•
•
•
•
•
Wide Analog Input Voltage Range. .
±5
V Max
Low ON Resistance
–
70
Ω
Typical (V
CC
–
V
EE
= 4.5 V)
–
40
Ω
Typical (V
CC
–
V
EE
= 9 V)
DESCRIPTION
Low Crosstalk Between Switches
These devices are digitally controlled analog switches
Fast Switching and Propagation Speeds
which utilize silicon gate CMOS technology to
Break-Before-Make Switching
achieve operating speeds similar to LSTTL with the
low power consumption of standard CMOS integrated
Wide Operating Temperature Range
circuits.
–55°C
to 125°C
These analog multiplexers/demultiplexers control
CD54HC/CD74HC Types
analog voltages that may vary across the voltage
–
Operation Control Voltage . . . . . . 2 V to 6 V
supply range (i.e., V
CC
to V
EE
). They are bidirectional
–
Switch Voltage . . . . . . . . . . . . . . 0 V to 10 V
switches thus allowing any analog input to be used as
«
an output and vice-versa. The switches have low ON
resistance and low OFF leakages. In addition, all
CD54HCT/CD74HCT Types
three devices have an enable control which, when
–
Operation Control Voltage . . . 4.5 V to 5.5 V
high, disables all switches to their OFF state.
–
Switch Voltage . . . . . . . . . . . . . . . 0 V to 10
V
ORDERING INFORMATION
(1)
PART NUMBER
TEMP. RANGE
(°C)
–55
to 125
–55
to 125
–55
to 125
–55
to 125
–55
to 125
–55
to 125
–55
to 125
–55
to 125
–55
to 125
–55
to 125
–55
to 125
–55
to 125
–55
to 125
–55
to 125
–55
to 125
–55
to 125
–55
to 125
–55
to 125
PACKAGE
16 Ld CERDIP
16 Ld CERDIP
16 Ld CERDIP
16 Ld CERDIP
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
16 Ld SOP
16 Ld TSSOP
16 Ld TSSOP
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
16 Ld SOP
16 Ld TSSOP
16 Ld TSSOP
–
Direct LSTTL Input Logic Compatibility
V
IL
= 0.8 V Max, V
IH
= 2 V Min
–
CMOS Input Compatibility
I
I
≤
1
μA
at V
OL
, V
OH
CD54HC4051F3A
CD54HC4052F3A
CD54HC4053F3A
CD54HCT4051F3A
CD74HC4051E
CD74HC4051M
CD74HC4051MT
CD74HC4051M96G3
CD74HC4051NSR
CD74HC4051PWR
CD74HC4051PWT
CD74HC4052E
CD74HC4052M
CD74HC4052MT
CD74HC4052M96G3
CD74HC4052NSR
CD74HC4052PW
CD74HC4052PWR
(1)
1
When ordering, use the entire part number. The suffixes 96 and R denote tape and reel. The suffix T denotes a small-quantity reel of
250.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
©
1997–2011, Texas Instruments Incorporated
CD/74HC4051, CD54/74HCT4051, CD54/74HC4052,
SCHS122J
–
NOVEMBER 1997
–
REVISED FEBRUARY 2011
www.ti.com
ORDERING INFORMATION
(1)
(continued)
PART NUMBER
CD74HC4052PWT
CD74HC4053E
CD74HC4053M
CD74HC4053MT
CD74HC4053M96G3
CD74HC4053NSR
CD74HC4053PW
CD74HC4053PWRG3
CD74HC4053PWT
CD74HCT4051E
CD74HCT4051M
CD74HCT4051MT
CD74HCT4051M96
CD74HCT4052E
CD74HCT4052M
CD74HCT4052MT
CD74HCT4052M96
CDHCT4053E
CDHCT4053M
CDHCT4053MT
CDHCT4053M96
CDHCT4053PWR
CDHCT4053PWT
TEMP. RANGE
(°C)
–55
to 125
–55
to 125
–55
to 125
–55
to 125
–55
to 125
–55
to 125
–55
to 125
–55
to 125
–55
to 125
–55
to 125
–55
to 125
–55
to 125
–55
to 125
–55
to 125
–55
to 125
–55
to 125
–55
to 125
–55
to 125
–55
to 125
–55
to 125
–55
to 125
–55
to 125
–55
to 125
PACKAGE
16 Ld TSSOP
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
16 Ld SOP
16 Ld TSSOP
16 Ld TSSOP
16 Ld TSSOP
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
16 Ld TSSOP
16 Ld TSSOP
2
Submit Documentation Feedback
©
1997–2011, Texas Instruments Incorporated
Product Folder Link(s):
CD/74HC4051, CD54/74HCT4051, CD54/74HC4052,
CD/74HC4051, CD54/74HCT4051, CD54/74HC4052,
www.ti.com
SCHS122J
–
NOVEMBER 1997
–
REVISED FEBRUARY 2011
CD54HC4051, CD54HCT4051
(CERDIP)
CD74HC4051
(PDIP, SOIC, SOP, TSSOP)
CD74HCT4051
(PDIP, SOIC)
TOP VIEW
CHANNEL
IN/OUT
COM OUT/IN
CHANNEL
IN/OUT
A4 1
A6 2
A 3
A7 4
A5 5
E 6
V
EE
7
16 V
CC
15 A2
14 A1
13 A0
12 A3
11 S0
10 S1
9 S2
ADDRESS
SELECT
CHANNEL
IN/OUT
CHANNEL
IN/OUT
CD54HC4052
(CERDIP)
CD74HC4052
(PDIP, SOIC, SOP, TSSOP)
CD74HCT4052
(PDIP, SOIC)
TOP VIEW
B0 1
B2 2
3
16 V
CC
15 A2
14 A1
13 A
N
12 A0
11 A3
10 S0
9 S1
CHANNEL
IN/OUT
COM OUT/IN
CHANNEL
IN/OUT
COM OUT/IN B
N
CHANNEL
IN/OUT
B3 4
B1 5
E 6
V
EE
GND
7
8
GND 8
CD54HC4053
(CERDIP)
CD74HC4053
(PDIP, SOIC, SOP, TSSOP)
CD74HCT4053
(PDIP, SOIC, TSSOP)
TOP VIEW
B1 1
CHANNEL
IN/OUT
B0 2
C1 3
COM OUT/IN C
N
4
16 V
CC
15 B
N
14 A
N
13 A1
12 A0
11 S0
10 S1
9 S2
COM OUT/IN
COM OUT/IN
CHANNEL
IN/OUT
IN/OUT C0 5
E 6
V
EE
GND
7
8
©
1997–2011, Texas Instruments Incorporated
Submit Documentation Feedback
3
Product Folder Link(s):
CD/74HC4051, CD54/74HCT4051, CD54/74HC4052,
CD/74HC4051, CD54/74HCT4051, CD54/74HC4052,
SCHS122J
–
NOVEMBER 1997
–
REVISED FEBRUARY 2011
www.ti.com
FUNCTIONAL DIAGRAM OF HC/HCT4051
CHANNEL IN/OUT
V
CC
16
A
7
4
A
6
2
A
5
5
A
4
1
A
3
12
A
2
15
A
1
14
A
0
13
TG
TG
S
0
11
TG
S
1
10
LOGIC
LEVEL
CONVERSION
BINARY
TO
1 OF 8
DECODER
WITH
ENABLE
TG
3
TG
A
COMMON
OUT/IN
S
2
9
TG
TG
E
6
TG
8
GND
7
V
EE
Table 1. TRUTH TABLE
'HC/CD74HCT4051
(1)
INPUT STATES
ENABLE
L
L
L
L
L
L
L
L
H
(1)
X = Don't care
S
2
L
L
L
L
H
H
H
H
X
S
1
L
L
H
H
L
L
H
H
X
S
0
L
H
L
H
L
H
L
H
X
A0
A1
A2
A3
A4
A5
A6
A7
None
ON CHANNELS
4
Submit Documentation Feedback
©
1997–2011, Texas Instruments Incorporated
Product Folder Link(s):
CD/74HC4051, CD54/74HCT4051, CD54/74HC4052,
CD/74HC4051, CD54/74HCT4051, CD54/74HC4052,
www.ti.com
SCHS122J
–
NOVEMBER 1997
–
REVISED FEBRUARY 2011
FUNCTIONAL DIAGRAM OF HC4052, CD74HCT4052
A CHANNELS IN/OUT
A
3
V
CC
16
TG
11
A
2
15
A
1
14
A
0
12
TG
TG
S
1
9
LOGIC
LEVEL
CONVERSION
BINARY
TO
1 OF 4
DECODER
WITH
ENABLE
TG
13
COMMON A
OUT/IN
COMMON B
OUT/IN
TG
3
S
0
10
TG
E
6
TG
TG
8
GND
7
V
EE
1
B
0
5
B
1
2
B
2
4
B
3
B CHANNELS IN/OUT
Table 2. FUNCTION TABLE
'HC4052,
CD74HCT4052
(1)
INPUT STATES
ENABLE
L
L
L
L
H
(1)
X = Don't care
S
1
L
L
H
H
X
S
0
L
H
L
H
X
A0, B0
A1, B1
A2, B2
A3, B3
None
ON CHANNELS
©
1997–2011, Texas Instruments Incorporated
Submit Documentation Feedback
5
Product Folder Link(s):
CD/74HC4051, CD54/74HCT4051, CD54/74HC4052,
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