DA6180.001
27 December, 2006
MAS6180
AM Receiver IC
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DESCRIPTION
The MAS6180 AM-Receiver chip is a highly sensitive,
simple to use AM receiver specially intended to receive
time signals in the frequency range from 40 kHz to 100
kHz. Only a few external components are required for
time signal receiver. The circuit has preamplifier, wide
range automatic gain control, demodulator and output
comparator built in. The output signal can be
processed directly by an additional digital circuitry to
extract the data from the received signal. The control
for AGC (automatic gain control) can be used to switch
AGC on or off if necessary.
MAS6180 has options for compensating shunt
capacitances of different crystals (See ordering
information on page 9).
Single Band Receiver IC
High Sensitivity
Very Low Power Consumption
Wide Supply Voltage Range
Power Down Control
Control for AGC On
High Selectivity by Crystal Filter
Fast Startup Feature
FEATURES
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Single Band Receiver IC
Highly Sensitive AM Receiver, 0.4
µV
RMS
typ.
Wide Supply Voltage Range from 1.1 V to 3.6 V
Very Low Power Consumption
Power Down Control
Fast Startup
Only a Few External Components Necessary
Control for AGC On
Wide Frequency Range from 40 kHz to 100 kHz
High Selectivity by Quartz Crystal Filter
Crystal Compensation Capacitance Options
Differential Input
APPLICATIONS
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Single Band Time Signal Receiver WWVB (USA),
JJY (Japan), DCF77 (Germany), MSF (UK), HGB
(Switzerland) and BPC (China)
BLOCK DIAGRAM
VDD
QOP
QI
QOM
AON
Demodulator
&
Comparator
OUT
RFIP
VDD
AGC Amplifier
RFIM
Power Supply/Biasing
VDD
VSS
PDN
AGC
DEC
1 (9)
DA6180.001
27 December, 2006
MAS6180 PAD LAYOUT
VSS pad
bonded
first!
1070
µ
m
VDD
QOP
QOM
QI
AGC
OUT
VSS
RFIM
RFIP
PDN
AON
DEC
MAS6180Ax,
x = 1, 2, 5
DIE size = 1.07 mm x 1.37 mm; PAD size = 80
µm
x 80
µm
Note:
Because the substrate of the die is internally connected to VSS, the die has to be connected to VSS or left
floating. Please make sure that VSS is the first pad to be bonded. Pick-and-place and all component assembly
are recommended to be performed in ESD protected area.
Note:
Coordinates are pad center points where origin has been located in bottom-left corner of the silicon die.
Pad Identification
Power Supply Voltage
Positive Quartz Filter Output for Crystal
Negative Quartz Filter Output for Crystal
Quartz Filter Input for Crystal and External
Compensation Capacitor
AGC Capacitor
Receiver Output
Demodulator Capacitor
AGC On Control
Power Down
Positive Receiver Input
Negative Receiver Input
Power Supply Ground
Name
VDD
QOP
QOM
QI
AGC
OUT
DEC
AON
PDN
RFIP
RFIM
VSS
X-coordinate
152
µm
152
µm
152
µm
152
µm
152
µm
152
µm
915
µm
915
µm
915
µm
915
µm
915
µm
915
µm
Y-coordinate
1137
µm
1002
µm
815
µm
629
µm
443
µm
257
µm
265
µm
451
µm
636
µm
824
µm
1010
µm
1158
µm
Note
1370
µ
m
1
2
3
4
5
5
Notes:
1) External crystal compensation capacitor pin QOM is connected only in MAS6180A5 version. It is left
unconnected in MAS6180A1 and A2 versions which have internal compensation capacitor.
2) OUT = VSS when carrier amplitude at maximum; OUT = VDD when carrier amplitude is reduced (modulated)
-
the output is a current source/sink with |I
OUT
| > 5
µA
-
at power down the output is pulled to VSS (pull down switch)
3) AON = VSS means AGC off (hold current gain level); AON = VDD means AGC on (working)
-
Internal pull-up with current < 1
µA
which is switched off at power down
4) PDN = VSS means receiver on; PDN = VDD means receiver off
Fast start-up is triggered when the receiver is after power down (PDN=VDD) controlled to power up
(PDN=VSS) i.e. at the falling edge of PDN signal.
5) Receiver inputs RFIP and RFIM have both 600 kΩ biasing resistors towards VDD
2 (9)
DA6180.001
27 December, 2006
6)
ABSOLUTE MAXIMUM RATINGS
All Voltages with Respect to Ground
Parameter
Supply Voltage
Input Voltage
ESD Rating
Symbol
V
DD
-V
SS
V
IN
V
ESD
Conditions
Min
- 0.3
V
SS
-0.3
±2
Max
5.5
V
DD
+0.3
Unit
V
V
kV
Latchup Current Limit
I
LUT
For all pins,
Human Body Model (HBM),
ESD Association Standard
Test Method ESD-STM5.1-
1998, C
ESD
= 100 pF,
Rs = 1500
Ω),
For all pins,
test according to
Micro Analog Systems
specification ESQ0141.
See note below.
±100
mA
Operating Temperature
Storage Temperature
T
OP
T
ST
-40
- 55
+85
+150
°
C
°
C
Stresses beyond those listed may cause permanent damage to the device. The device may not operate under these conditions, but it will
not be destroyed.
Note:
In latchup testing the supply voltages are connected normally to the tested device. Then pulsed test current is fed to each input
separately and device current consumption is observed. If the device current consumption increases suddenly due to test current pulses
and the abnormally high current consumption continues after test current pulses are cut off then the device has gone to latch up. Current
pulse is turned on for 10 ms and off for 20 ms.
ELECTRICAL CHARACTERISTICS
Operating Conditions: VDD = 1.5V, Temperature = 25° unless otherwise specified.
C,
Parameter
Operating Voltage
Current Consumption
Symbol
V
DD
I
DD
Conditions
VDD=1.5 V, Vin=0
µVrms
VDD=1.5 V, Vin=20 mVrms
VDD=3.6 V, Vin=0
µVrms
VDD=3.6 V, Vin=20 mVrms
See note below.
Min
1.10
40
24
Typ
55
40
58
43
Max
3.6
80
65
Unit
V
µA
Stand-By Current
Input Frequency Range
Minimum Input Voltage
Maximum Input Voltage
Receiver Input Resistance
Receiver Input Capacitance
Input Levels |l
IN
|<0.5
µA
Output Current
V
OL
<0.2 V
DD
;V
OH
>0.8 V
DD
Output Pulse
I
DDoff
f
IN
V
IN min
V
IN max
R
RFI
C
RFI
V
IL
V
IH
|I
OUT
|
T
100ms
T
200ms
T
500ms
T
800ms
40
0.4
20
Differential Input,
f=40 kHz..77.5 kHz
V
DD
-0.35
5
1
µVrms ≤
V
IN
≤
20 mVrms
1
µVrms ≤
V
IN
≤
20 mVrms
1
µVrms ≤
V
IN
≤
20 mVrms
1
µVrms ≤
V
IN
≤
20 mVrms
Fast Start-up, Vin=0.4
µVrms
Fast Start-up, Vin=20 mVrms
50
150
400
700
500
800
1.3
3.5
50
600
0.5
0.1
100
1
µA
kHz
µVrms
mVrms
kΩ
pF
V
µA
0.35
140
230
600
900
ms
ms
ms
ms
s
Startup Time
Output Delay Time
T
Start
T
Delay
100
ms
Note:
Stand-by current consumption may increase if V
IH
and V
IL
differ from VDD and 0 respectively.
3 (9)
DA6180.001
27 December, 2006
TYPICAL APPLICATION
Note 1
MAS6180A1, A2
VDD
Note 4
Optional
Control
for AGC on/hold
QI
QOM
AON
Demodulator
&
Comparator
OUT
Receiver
Output
Note 5
RFIP
Ferrite
Antenna
VDD
QOP
AGC Amplifier
RFIM
VDD
Power Supply/Biasing
VDD
VSS
PDN
AGC
C
AGC
10
µ
F
VDD
DEC
C
DEC
47 nF
VDD
VDD
AGC
C
AGC
+
10
µ
F
Note 2
DEC
C
DEC
47 nF
1.4 V
GND
OR
Note 3
Power Down /
Fast Startup
Control
Note 2
Figure 1.
Application circuit of internal compensation capacitance option version MAS6180A1 and A2.
Note 1
C
C_EXT
=C
0
MAS6180A5
VDD
Note 4
Optional
Control
for AGC on/hold
AON
Demodulator
&
Comparator
OUT
Receiver
Output
Note 5
RFIP
Ferrite
Antenna
VDD
QOP
QI
QOM
AGC Amplifier
RFIM
VDD
Power Supply/Biasing
VDD
VSS
PDN
AGC
C
AGC
10
µ
F
DEC
C
DEC
47 nF
VDD
VDD
AGC
C
AGC
+
10
µ
F
Note 2
Note 2
DEC
C
DEC
47 nF
1.4 V
GND
VDD
OR
Note 3
Power Down /
Fast Startup
Control
Figure 2.
Application circuit of external compensation capacitance option version MAS6180A5.
4 (9)
DA6180.001
27 December, 2006
TYPICAL APPLICATION (Continued)
Note 1
Note 4
Optional
Control
for AGC on/hold
QI
QOM
AON
Demodulator
&
Comparator
OUT
Receiver
Output
MAS6180A5
VDD
Note 5
RFIP
Ferrite
Antenna
VDD
QOP
AGC Amplifier
RFIM
Antenna
Frequency
Selection
VDD
Power Supply/Biasing
VDD
VSS
PDN
AGC
C
AGC
10
µ
F
DEC
C
DEC
47 nF
AGC
C
AGC
10
µ
F
+
DEC
C
DEC
47 nF
OR
1.4 V
GND
VDD
Note 3
Power Down /
Fast Startup
Control
Note 2
VDD
VDD
Note 2
Figure 3.
Dual band application circuit of external compensation capacitance option version MAS6180A5. PMOS
switch transistor is used since RFIM input is biased close to VDD voltage.
5 (9)
stm32/stm8
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