SN54F32, SN74F32
QUADRUPLE 2-INPUT POSITIVE-OR GATES
SDFS044B – MARCH 1987 – REVISED MAY 1999
D
Package Options Include Plastic
Small-Outline (D) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) DIPs
SN54F32 . . . J PACKAGE
SN74F32 . . . D OR N PACKAGE
(TOP VIEW)
description
These devices contain four independent 2-input
OR gates. They perform the Boolean functions
Y = A + B or Y = A
•
B in positive logic.
The SN54F32 is characterized for operation over
the full military temperature range of –55°C to
125°C. The SN74F32 is characterized for
operation from 0°C to 70°C.
FUNCTION TABLE
(each gate)
INPUTS
A
H
X
L
B
X
H
L
OUTPUT
Y
H
H
L
1A
1B
1Y
2A
2B
2Y
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
4B
4A
4Y
3B
3A
3Y
SN54F32 . . . FK PACKAGE
(TOP VIEW)
1B
1A
NC
V
CC
4B
1Y
NC
2A
NC
2B
3
4
5
6
7
8
2 1 20 19
18
17
16
15
14
9 10 11 12 13
4A
NC
4Y
NC
3B
NC – No internal connection
logic symbol
†
1A
1B
2A
2B
3A
3B
4A
4B
1
2
4
5
9
10
12
13
11
4Y
8
3Y
≥1
3
1Y
6
2Y
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
logic diagram, each gate (positive logic)
A
B
Y
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
©
1999, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
2Y
GND
NC
3Y
3A
1
SN54F32, SN74F32
QUADRUPLE 2-INPUT POSITIVE-OR GATES
SDFS044B – MARCH 1987 – REVISED MAY 1999
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, V
I
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1.2 V to 7 V
Input current range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –30 mA to 5 mA
Voltage range applied to any output in the high state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
CC
Current into any output in the low state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 mA
Package thermal impedance,
θ
JA
(see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input voltage ratings may be exceeded provided the input current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
recommended operating conditions (see Note 3)
SN54F32
MIN
VCC
VIH
VIL
IIK
IOH
IOL
Supply voltage
High-level input voltage
Low-level input voltage
Input clamp current
High-level output current
Low-level output current
4.5
2
0.8
–18
–1
20
NOM
5
MAX
5.5
MIN
4.5
2
0.8
–18
–1
20
SN74F32
NOM
5
MAX
5.5
UNIT
V
V
V
mA
mA
mA
TA
Operating free-air temperature
–55
125
0
70
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs,
literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VOH
VOL
II
IIH
IIL
IOS§
ICCH¶
VCC = 4.5 V,
VCC = 4.5 V,
VCC = 4.75 V,
VCC = 4.5 V,
VCC = 5.5 V,
VCC = 5.5 V,
VCC = 5.5 V,
VCC = 5.5 V,
VCC = 5.5 V
VCC = 5.5 V,
TEST CONDITIONS
II = –18 mA
IOH = –1 mA
IOH = –1 mA
IOL = 20 mA
VI = 7 V
VI = 2.7 V
VI = 0.5 V
VO = 0
–60
6.1
SN54F32
MIN TYP‡
MAX
–1.2
2.5
3.4
0.3
0.5
0.1
20
–0.6
–150
9.2
–60
6.1
2.5
2.7
0.3
0.5
0.1
20
–0.6
–150
9.2
15.5
3.4
SN74F32
MIN TYP‡
MAX
–1.2
UNIT
V
V
V
mA
µA
mA
mA
mA
mA
ICCL
VI = 0
10.3
15.5
10.3
‡ All typical values are at VCC = 5 V, TA = 25°C.
§ Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
¶ ICCH is measured with one input per gate at 4.5 V and all others grounded.
2
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
SN54F32, SN74F32
QUADRUPLE 2-INPUT POSITIVE-OR GATES
SDFS044B – MARCH 1987 – REVISED MAY 1999
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
PARAMETER
tPLH
tPHL
FROM
(INPUT)
TO
(OUTPUT)
VCC = 5 V,
TA = 25°C
MIN
2.2
2.2
TYP
3.8
3.6
MAX
5.6
5.3
SN54F32
MIN
2.2
1.7
MAX
7.5
7.5
SN74F32
MIN
2.2
2.2
MAX
6.6
6.3
ns
UNIT
A or B
Y
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
3
SN54F32, SN74F32
QUADRUPLE 2-INPUT POSITIVE-OR GATES
SDFS044B – MARCH 1987 – REVISED MAY 1999
PARAMETER MEASUREMENT INFORMATION
500
Ω
S1
7V
Open
From Output
Under Test
CL
(see Note A)
Test
Point
500
Ω
From Output
Under Test
CL
(see Note A)
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Collector
S1
Open
7V
Open
7V
500
Ω
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
3V
Timing Input
tw
3V
tsu
Data Input
0V
1.5 V
1.5 V
0V
th
3V
1.5 V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3V
3V
1.5 V
tPZL
1.5 V
tPZH
VOH
1.5 V
1.5 V
VOL
Output
Waveform 2
S1 at GND
(see Note B)
1.5 V
1.5 V
0V
tPLZ
≈
3.5 V
VOL + 0.3 V
tPHZ
VOH – 0.3 V
VOH
≈
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
VOL
Input
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
Input
tPLH
In-Phase
Output
tPHL
Out-of-Phase
Output
1.5 V
1.5 V
0V
tPHL
1.5 V
1.5 V
VOH
VOL
tPLH
Output
Control
Output
Waveform 1
S1 at 7 V
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
≤
1 MHz, ZO = 50
Ω,
tr
≤
2.5 ns, tf
≤
2.5 ns,
duty cycle = 50%.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
4
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
PACKAGING INFORMATION
Orderable Device
5962-9758801Q2A
Status
(1)
Package Type Package Pins Package
Drawing
Qty
LCCC
FK
20
1
Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C)
-55 to 125
Device Marking
(4/5)
Samples
ACTIVE
TBD
POST-PLATE
N / A for Pkg Type
5962-
9758801Q2A
SNJ54F
32FK
5962-9758801QC
A
SNJ54F32J
5962-9758801QD
A
SNJ54F32W
SN54F32J
F32
F32
F32
F32
F32
SN74F32N
5962-9758801QCA
ACTIVE
CDIP
J
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9758801QDA
ACTIVE
CFP
W
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
SN54F32J
SN74F32D
SN74F32DG4
SN74F32DR
SN74F32DRE4
SN74F32DRG4
SN74F32N
SN74F32N3
SN74F32NE4
SN74F32NSR
SNJ54F32FK
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
OBSOLETE
ACTIVE
ACTIVE
ACTIVE
CDIP
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
PDIP
SO
LCCC
J
D
D
D
D
D
N
N
N
NS
FK
14
14
14
14
14
14
14
14
14
14
20
1
50
50
2500
2500
2500
25
TBD
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Pb-Free
(RoHS)
TBD
Pb-Free
(RoHS)
Green (RoHS
& no Sb/Br)
TBD
A42
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Call TI
CU NIPDAU
CU NIPDAU
POST-PLATE
N / A for Pkg Type
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
Call TI
N / A for Pkg Type
Level-1-260C-UNLIM
N / A for Pkg Type
-55 to 125
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
-55 to 125
25
2000
1
SN74F32N
74F32
5962-
9758801Q2A
SNJ54F
32FK
5962-9758801QC
A
SNJ54F32J
ACTIVE
CDIP
J
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
Addendum-Page 1
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