CD54HC173, CD74HC173,
CD54HCT173, CD74HCT173
Data sheet acquired from Harris Semiconductor
SCHS158E
February 1998 - Revised October 2003
High-Speed CMOS Logic
Quad D-Type Flip-Flop, Three-State
Description
The ’HC173 and ’HCT173 high speed three-state quad D-
type flip-flops are fabricated with silicon gate CMOS technol-
ogy. They possess the low power consumption of standard
CMOS Integrated circuits, and can operate at speeds com-
parable to the equivalent low power Schottky devices. The
buffered outputs can drive 15 LSTTL loads. The large output
drive capability and three-state feature make these parts ide-
ally suited for interfacing with bus lines in bus oriented sys-
tems.
The four D-type flip-flops operate synchronously from a com-
mon clock. The outputs are in the three-state mode when
either of the two output disable pins are at the logic “1” level.
The input ENABLES allow the flip-flops to remain in their
present states without having to disrupt the clock If either of
the 2 input ENABLES are taken to a logic “1” level, the Q
outputs are fed back to the inputs, forcing the flip-flops to
remain in the same state. Reset is enabled by taking the
MASTER RESET (MR) input to a logic “1” level. The data
outputs change state on the positive going edge of the clock.
The ’HCT173 logic family is functionally, as well as pin com-
patible with the standard LS logic family
.
Features
• Three-State Buffered Outputs
[ /Title
(CD74H
C173,
CD74H
CT173)
/Subject
(High
Speed
CMOS
Logic
Quad D-
Type
• Gated Input and Output Enables
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55
o
C to 125
o
C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30% of V
CC
at V
CC
= 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
IL
= 0.8V (Max), V
IH
= 2V (Min)
- CMOS Input Compatibility, I
l
≤
1µA at V
OL
, V
OH
Pinout
CD54HC173, CD54HCT173
(CERDIP)
CD74HC173
(PDIP, SOIC, SOP, TSSOP)
CD74HCT173
(PDIP, SOIC)
TOP VIEW
OE 1
OE2 2
Q
0
3
Q
1
4
Q
2
5
Q
3
6
CP 7
GND 8
16 V
CC
15 MR
14 D0
13 D1
12 D2
11 D3
10 E2
9 E1
Ordering Information
PART NUMBER
CD54HC173F3A
CD54HCT173F3A
CD74HC173E
CD74HC173M
CD74HC173MT
CD74HC173M96
CD74HC173NSR
CD74HC173PW
CD74HC173PWR
CD74HC173PWT
CD74HCT173E
CD74HCT173M
CD74HCT173MT
CD74HCT173M96
TEMP. RANGE
(
o
C)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
PACKAGE
16 Ld CERDIP
16 Ld CERDIP
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
16 Ld SOP
16 Ld TSSOP
16 Ld TSSOP
16 Ld TSSOP
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
©
2003, Texas Instruments Incorporated
1
CD54HC173, CD74HC173, CD54HCT173, CD74HCT173
Functional Diagram
E1
E2
10
D0
D1
D2
11
D3
7
CP
MR
OE1
OE2
15
1
2
6
Q
3
14
13
4
12
5
Q
2
Q
1
9
3
Q
0
TRUTH TABLE
INPUTS
DATA ENABLE
MR
H
L
L
L
L
L
CP
X
L
↑
↑
↑
↑
E1
X
X
H
X
L
L
E2
X
X
X
H
L
L
DATA
D
X
X
X
X
L
H
OUTPUT
Q
n
L
Q
0
Q
0
Q
0
L
H
H= High Voltage Level
L = Low Voltage Level
X= Irrelevant
↑=
Transition from Low to High Level
Q
0
= Level Before the Indicated Steady-State Input Conditions Were
Established
NOTE:
1. When either OE1 or OE2 (or both) is (are) high, the output is dis-
abled to the high-impedance state, however, sequential opera-
tion of the flip-flops is not affected.
2
CD54HC173, CD74HC173, CD54HCT173, CD74HCT173
Logic Diagram
9
E1
10
E2
D
14
D0
7
CP
CP
R
15
MR
1
OE1
Q
N
Q
V
CC
P
3
Q
0
2
OE2
13
D1
12
D2
11
D3
3 CIRCUITS IDENTICAL TO ABOVE CIRCUIT
IN DASHED ENCLOSURE
4
5
6
Q
3
Q
1
Q
2
3
CD54HC173, CD74HC173, CD54HCT173, CD74HCT173
Absolute Maximum Ratings
DC Supply Voltage, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, I
IK
For V
I
< -0.5V or V
I
> V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, I
OK
For V
O
< -0.5V or V
O
> V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . .±20mA
DC Output Source or Sink Current per Output Pin, I
O
For V
O
> -0.5V or V
O
< V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . .±25mA
DC V
CC
or Ground Current, I
CC
. . . . . . . . . . . . . . . . . . . . . . . . .±70mA
Thermal Information
Package Thermal Impedance,
θ
JA
(see Note 2):
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
o
C/W
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
o
C/W
NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
ο
C/W
PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . 108
o
C/W
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . .-65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300
o
C
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range (T
A
) . . . . . . . . . . . . . . . . . . . . . -55
o
C to 125
o
C
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V
I
, V
O
. . . . . . . . . . . . . . . . . 0V to V
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
2. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST
CONDITIONS
PARAMETER
HC TYPES
High Level Input
Voltage
V
IH
-
-
2
4.5
6
Low Level Input
Voltage
V
IL
-
-
2
4.5
6
High Level Output
Voltage
CMOS Loads
V
OH
V
IH
or
V
IL
-0.02
-0.02
-0.02
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
V
OL
V
IH
or
V
IL
-6
-7.8
0.02
0.02
0.02
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
Quiescent Device
Current
I
I
I
CC
V
CC
or
GND
V
CC
or
GND
6
7.8
-
0
2
4.5
6
4.5
6
2
4.5
6
4.5
6
6
6
1.5
3.15
4.2
-
-
-
1.9
4.4
5.9
3.98
5.48
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.5
1.35
1.8
-
-
-
-
-
0.1
0.1
0.1
0.26
0.26
±0.1
8
1.5
3.15
4.2
-
-
-
1.9
4.4
5.9
3.84
5.34
-
-
-
-
-
-
-
-
-
-
0.5
1.35
1.8
-
-
-
-
-
0.1
0.1
0.1
0.33
0.33
±1
80
1.5
3.15
4.2
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
-
-
-
-
-
0.5
1.35
1.8
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
±1
160
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
µA
SYMBOL
V
I
(V)
I
O
(mA) V
CC
(V)
MIN
25
o
C
TYP
MAX
-40
o
C TO 85
o
C
MIN
MAX
-55
o
C TO 125
o
C
MIN
MAX
UNITS
4
CD54HC173, CD74HC173, CD54HCT173, CD74HCT173
DC Electrical Specifications
(Continued)
TEST
CONDITIONS
PARAMETER
Three-State Leakage
Current
HCT TYPES
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
CMOS Loads
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
Quiescent Device
Current
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
Three-State Leakage
Current
NOTE:
3. For dual-supply systems theoretical worst case (V
I
= 2.4V, V
CC
= 5.5V) specification is 1.8mA.
I
I
I
CC
∆I
CC
(Note 3)
I
OZ
V
CC
to
GND
V
CC
or
GND
V
CC
-2.1
V
IL
or
V
IH
V
OL
V
IH
or
V
IL
V
IH
V
IL
V
OH
-
-
V
IH
or
V
IL
-
-
-0.02
4.5 to
5.5
4.5 to
5.5
4.5
2
-
4.4
-
-
-
-
0.8
-
2
-
4.4
-
0.8
-
2
-
4.4
-
0.8
-
V
V
V
SYMBOL
I
OZ
V
I
(V)
V
IL
or
V
IH
I
O
(mA) V
CC
(V)
-
6
MIN
-
25
o
C
TYP
-
MAX
±0.5
-40
o
C TO 85
o
C
MIN
-
MAX
±0.5
-55
o
C TO 125
o
C
MIN
-
MAX
±10
UNITS
µA
-6
4.5
3.98
-
-
3.84
-
3.7
-
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
6
4.5
-
-
0.26
-
0.33
-
0.4
V
0
0
-
5.5
5.5
4.5 to
5.5
5.5
-
-
-
-
-
100
±0.1
8
360
-
-
-
±1
80
450
-
-
-
±1
160
490
µA
µA
µA
-
-
-
±0.5
-
±5.0
-
±10
µA
HCT Input Loading Table
INPUT
D0-D3
E1 and E2
CP
MR
OE1 and OE2
UNIT LOADS
0.15
0.15
0.25
0.2
0.5
NOTE: Unit Load is
∆I
CC
limit specified in DC Electrical
Specifications table, e.g., 360µA max at 25
o
C.
5
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