DRAM MODULE
KMM5361205C2W/C2WG
1Mx36 DRAM SIMM
(1MX16 Base)
Revision 0.0
November 1997
-1-
Rev. 0.0 (Nov. 1997)
DRAM MODULE
Revision History
Version 0.0 (November 1997)
• Changed module PCB from 6-Layer to 4-Layer.
KMM5361205C2W/C2WG
• Changed Module Part No. from KMM5361205CW/CWG to KMM5361205C2W/C2WG caused by PCB revision .
-2-
Rev. 0.0 (Nov. 1997)
DRAM MODULE
KMM5361205C2W/C2WG
KMM5361205C2W/C2WG Fast Page Mode with Extended Data Out
1M x 36 DRAM SIMM using 1Mx16 and 4M Quad CAS EDO, 1K Refresh,
GENERAL DESCRIPTION
The Samsung KMM5361205C2W is a 1Mx36bits Dynamic
RAM high density memory module. The Samsung
KMM5361205C2W consists of two CMOS 1Mx16bits DRAMs in
42-pin SOJ package and one CMOS 1Mx4 bit Quad CAS with
EDO DRAM in 24-pin SOJ package mounted on a 72-pin glass-
epoxy substrate. A 0.1 or 0.22uF decoupling capacitor is
mounted on the printed circuit board for each DRAM. The
KMM5361205C2W is a Single In-line Memory Module with edge
connections and is intended for mounting into 72 pin edge con-
nector sockets.
FEATURES
• Part Identification
- KMM5361205C2W(1024 cycles/16ms Ref, SOJ, Solder)
- KMM5361205C2WG(1024 cycles/16ms Ref, SOJ, Gold)
• Fast Page Mode with Extended Data Out
• CAS-before-RAS refresh capability
• RAS-only and hidden refresh capability
• TTL compatible inputs and outputs
• Single +5V±10% power supply
• JEDEC standard PDPin & pinout
• PCB : Height(750mil), single sided component
PERFORMANCE RANGE
Speed
-5
-6
t
RAC
50ns
60ns
t
CAC
15ns
17ns
t
RC
90ns
110ns
t
HPC
25ns
30ns
PIN CONFIGURATIONS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Symbol
V
SS
DQ0
DQ18
DQ1
DQ19
DQ2
DQ20
DQ3
DQ21
Vcc
NC
A0
A1
A2
A3
A4
A5
A6
Res(A10)
DQ4
DQ22
DQ5
DQ23
DQ6
DQ24
DQ7
DQ25
A7
Res(A11)
Vcc
A8
A9
Res(RAS1)
RAS0
DQ26
DQ8
Pin
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Symbol
DQ17
DQ35
Vss
CAS0
CAS2
CAS3
CAS1
RAS0
Res(RAS1)
NC
W
NC
DQ9
DQ27
DQ10
DQ28
DQ11
DQ29
DQ12
DQ30
DQ13
DQ31
Vcc
DQ32
DQ14
DQ33
DQ15
DQ34
DQ16
NC
PD1
PD2
PD3
PD4
NC
Vss
PIN NAMES
Pin Name
A0 - A9
DQ0 - DQ35
W
RAS0
CAS0 - CAS3
PD1 -PD4
Vcc
Vss
NC
Res
Function
Address Inputs
Data In/Out
Read/Write Enable
Row Address Strobe
Column Address Strobe
Presence Detect
Power(+5V)
Ground
No Connection
Reserved Pin
PRESENCE DETECT PINS (Optional)
Pin
PD1
PD2
PD3
PD4
50NS
Vss
Vss
Vss
Vss
60NS
Vss
Vss
NC
NC
* Pin connection changing available
SAMSUNG ELECTRONICS CO., LTD.
reserves the right to
change products and specifications without notice.
-3-
Rev. 0.0 (Nov. 1997)
DRAM MODULE
FUNCTIONAL BLOCK DIAGRAM
KMM5361205C2W/C2WG
RAS0
RAS
CAS0
LCAS
U0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
CAS1
UCAS
OE
W
A0-A9
RAS
CAS0
CAS1
U2
CAS2
CAS3
OE
W A0-A9
DQ0
DQ1
DQ2
DQ3
DQ8
DQ17
DQ26
DQ35
RAS
CAS2
LCAS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
CAS3
UCAS
OE
W
W
A0-A9
Vcc
A0-A9
.1 or .22uF Capacitor
for each DRAM
Vss
To all DRAMs
-4-
Rev. 0.0 (Nov. 1997)
DRAM MODULE
ABSOLUTE MAXIMUM RATINGS *
Item
Voltage on any pin relative to V
SS
Voltage on V
CC
supply relative to V
SS
Storage Temperature
Power Dissipation
Short Circuit Output Current
Symbol
V
IN
, V
OUT
V
CC
T
stg
P
d
I
OS
KMM5361205C2W/C2WG
Rating
-1 to +7.0
-1 to +7.0
-55 to +150
3
50
Unit
V
V
°C
W
mA
* Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for in tended
periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltage referenced to V
SS
, T
A
= 0 to 70°C)
Item
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
*1 : V
CC
+2.0V/20ns, Pulse width is measured at V
CC
.
*2 : -2.0V/20ns, Pulse width is measured at V
SS
.
Symbol
V
CC
V
SS
V
IH
V
IL
Min
4.5
0
2.4
-1.0
*2
Typ
5.0
0
-
-
Max
5.5
0
V
CC
+1
*1
0.8
Unit
V
V
V
V
DC AND OPERATING CHARACTERISTICS
(Recommended operating conditions unless otherwise noted)
Symbol
I
CC1
I
CC2
I
CC3
I
CC4
I
CC5
I
CC6
I
I(L)
I
O(L)
V
OH
V
OL
I
CC1
I
CC2
I
CC3
I
CC4
I
CC5
I
CC6
I
I(L)
I
O(L)
V
OH
V
OL
Speed
-5
-6
Don′t care
-5
-6
-5
-6
Don′t care
-5
-6
Don′t care
Don′t care
KMM5321205C2W/C2WG
Min
-
-
Max
385
355
6
385
355
325
295
3
385
355
15
5
-
0.4
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
uA
uA
V
V
-
-
-
-
-
-
-
-
-15
-5
2.4
-
: Operating Current * ( RAS, CAS, Address cycling @
t
RC
=min)
: Standby Current ( RAS=CAS=W=V
IH
)
: RAS Only Refresh Current * ( CAS=V
IH
, RAS cycling @
t
RC
=min)
: EDO Mode Current * ( RAS=V
IL
, CAS cycling :
t
HPC
=min)
: Standby Current ( RAS=CAS=W=Vcc-0.2V)
: CAS-Before-RAS Refresh Current * ( RAS and CAS cycling @
t
RC
=min)
: Input Leakage Current (Any input 0
≤V
IN
≤Vcc+0.5V,
all other pins not under test=0 V)
: Output Leakage Current(Data Out is disabled, 0V
≤V
OUT
≤Vcc)
: Output High Voltage Level (I
OH
= -5mA)
: Output Low Voltage Level (I
OL
= 4.2mA)
* NOTE
: I
CC1
, I
CC3
, I
CC4
and I
CC6
are dependent on output loading and cycle rates. Specified values are obtained with the output open.
I
CC
is specified as an average current. In I
CC1
and I
CC3
, address can be changed maximum once while RAS=V
IL
. In I
CC4
,
address can be changed maximum once within one EDO mode cycle,
t
HPC.
-5-
Rev. 0.0 (Nov. 1997)
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