See Package Number N08E (N), M08A (M8), and MTC08 (MT8)
Pin Names
/CS
SO
/WP
V
SS
SI
SCK
/HOLD
V
CC
Chip Select Input
Serial Data Output
Write Protect
Ground
Serial Data Input
Serial Clock Input
Suspends Serial Data
Power Supply
Ordering Information
FM
25
C
XX
U
LZ
E
XX
Package
Letter Description
N
M8
MT8
None
V
E
Blank
L
LZ
Ultralite
Density/Mode
Interface
041
C
25
FM
8-pin DIP
8-pin SO
8-pin TSSOP
0 to 70°C
-40 to +125°C
-40 to +85°C
4.5V to 5.5V
2.7V to 5.5V
2.7V to 5.5V and
<1µA Standby Current
CS100UL Process
4K, mode 1
CMOS technology
SPI
Fairchild Nonvolatile
Memory Prefix
Temp. Range
Voltage Operating Range
2
FM25C041U Rev. B
www.fairchildsemi.com
FM25C041U 4K-Bit SPI Interface Serial CMOS EEPROM
Standard Voltage 4.5
≤
V
CC
≤
5.5V Specifications
Operating Conditions
Absolute Maximum Ratings
(Note 1)
Ambient Storage Temperature
All Input or Output Voltage with
Respect to Ground
Lead Temp. (Soldering, 10 sec.)
ESD Rating
-65°C to +150°C
+6.5V to -0.3V
+300°C
2000V
Ambient Operating Temperature
FM25C041U
FM25C041UE
FM25C041UV
Power Supply (V
CC
)
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
4.5V to 5.5V
DC and AC Electrical Characteristics
4.5V
≤
V
CC
≤
5.5V (unless otherwise specified)
Symbol
I
CC
I
CCSB
I
IL
I
OL
V
IL
V
IH
V
OL
V
OH
f
OP
t
RI
t
FI
t
CLH
t
CLL
t
CSH
t
CSS
t
DIS
t
HDS
t
CSN
t
DIN
t
HDN
t
PD
t
DH
t
LZ
t
DF
t
HZ
t
WP
Parameter
Operating Current
Standby Current
Input Leakage
Output Leakage
CMOS Input Low Voltage
CMOS Input High Voltage
Output Low Voltage
Output High Voltage
SCK Frequency
Input Rise Time
Input Fall Time
Clock High Time
Clock Low Time
Min /CS High Time
/CS Setup Time
Data Setup Time
/HOLD Setup Time
/CS Hold Time
Data Hold Time
/HOLD Hold Time
Output Delay
Output Hold Time
/HOLD to Output Low Z
Output Disable Time
/HOLD to Output High Z
Write Cycle Time
Conditions
/CS = V
IL
/CS = V
CC
V
IN
= 0 to V
CC
V
OUT
= GND to V
CC
Min
Max
3
50
Units
mA
µA
µA
µA
V
V
V
V
MHz
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
-1
-1
-0.3
0.7 * V
CC
+1
+1
V
CC
* 0.3
V
CC
+ 0.3
0.4
I
OL
= 1.6 mA
I
OH
= -0.8 mA
V
CC
- 0.8
2.1
2.0
2.0
(Note 2)
(Note 2)
(Note 3)
190
190
240
240
100
90
240
100
90
C
L
= 200 pF
0
100
C
L
= 200 pF
1–16 Bytes
240
100
10
240
ns
ns
ns
ns
ns
ms
Capacitance
T
A
= 25°C, f = 2.1/1 MHz (Note 4)
Symbol
C
OUT
C
IN
AC Test Conditions
Output Load
Input Pulse Levels
Timing Measurement Reference Level
C
L
= 200 pF
0.1 * V
CC
– 0.9 * V
CC
0.3 * V
CC
- 0.7 * V
CC
Test
Output Capacitance
Input Capacitance
Typ Max Units
3
2
8
6
pF
pF
Note 1:
Stress above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the
device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Note 2:
The f
OP
frequency specification specifies a minimum clock period of 1/f
OP
. Therefore, for every f
OP
clock cycle, t
CLH
+ t
CLL
must be equal to or greater than 1/f
OP
. For
example, for a f
OP
of 2.1MHz, the period equals 476ns. In this case if t C
LH
= is set to 190ns, then t
CLL
must be set to a minimum of 286ns.
Note 3:
/CS must be brought high for a minimum of t
CSH
between consecutive instruction cycles.
Note 4:
This parameter is periodically sampled and not 100% tested.
3
FM25C041U Rev. B
www.fairchildsemi.com
FM25C041U 4K-Bit SPI Interface Serial CMOS EEPROM
Low Voltage 2.7V
≤
V
CC
≤
4.5V Specifications
Operating Conditions
Absolute Maximum Ratings
(Note 5)
Ambient Storage Temperature
All Input or Output Voltage with
Respect to Ground
Lead Temp. (Soldering, 10 sec.)
ESD Rating
-65°C to +150°C
+6.5V to -0.3V
+300°C
2000V
Ambient Operating Temperature
FM25C041UL/LZ
FM25C041ULE/LZE
FM25C041ULV
Power Supply (V
CC
)
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
2.7V–4.5V
DC and AC Electrical Characteristics
2.7V
≤
V
CC
≤
4.5V (unless otherwise specified)
25C041UL/LE
25C041ULZ/ZE
Symbol
I
CC
I
CCSB
I
IL
I
OL
V
IL
V
IH
V
OL
V
OH
f
OP
t
RI
t
FI
t
CLH
t
CLL
t
CSH
t
CSS
t
DIS
t
HDS
t
CSN
t
DIN
t
HDN
t
PD
t
DH
t
LZ
t
DF
t
HZ
t
WP
25C041ULV
Min
Max
3
10
N/A
-1
-1
-0.3
V
CC
* 0.7
V
CC
- 0.8
1
1
V
CC
* 0.3
V
CC
+ 0.3
0.4
1.0
2.0
2.0
410
410
500
500
100
240
500
100
240
Parameter
Operating Current
Standby Current
Input Leakage
Output Leakage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
SCK Frequency
Input Rise Time
Input Fall Time
Clock High Time
Clock Low Time
Min. /CS High Time
/CS Setup Time
Data Setup Time
/HOLD Setup Time
/CS Hold Time
Data Hold Time
/HOLD Hold Time
Output Delay
Output Hold Time
/HOLD Output Low Z
Output Disable Time
/HOLD to Output Hi Z
Write Cycle Time
Part
L
LZ
Conditions
/CS = V
IL
/CS = V
CC
V
IN
= 0 to V
CC
V
OUT
= GND to V
CC
Min.
Max.
3
10
1
Units
mA
µA
µA
µA
µA
V
V
V
V
MHz
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
-1
-1
-0.3
V
CC
* 0.7
1
1
V
CC
* 0.3
V
CC
+ 0.3
0.4
I
OL
= 0.8 mA
I
OH
= –0.8 mA
V
CC
- 0.8
1.0
2.0
2.0
(Note 6)
(Note 6)
(Note 7)
410
410
500
500
100
240
500
100
240
C
L
= 200 pF
0
240
C
L
= 200 pF
1-16 Bytes
500
240
15
500
0
500
240
500
240
15
ns
ns
ns
ns
ns
ms
Capacitance
T
A
= 25°C, f = 2.1/1 MHz (Note 8)
Symbol
C
OUT
C
IN
AC Test Conditions
Output Load
Input Pulse Levels
Timing Measurement Reference Level
C
L
= 200pF
0.1 * V
CC
- 0.9 * V
CC
0.3 * V
CC
- 0.7 * V
CC
Test
Output Capacitance
Input Capacitance
Typ Max Units
3
2
8
6
pF
pF
Note 5:
Stress above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device
at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
Note 6:
The f
OP
frequency specification specifies a minimum clock period of 1/f
OP
. Therefore, for every f
OP
clock cycle, t
CLH
+ t
CLL
must be equal to or greater than 1/f
OP
. For
example, for a f
OP
of 1MHz, the period equals 1000ns. In this case if t
CLH
= is set to 410ns, then t
CLL
must be set to a minimum of 590ns.
Note 7:
/CS must be brought high for a minimum of t
CSH
between consecutive instruction cycles.
Note 8:
This parameter is periodically sampled and not 100% tested.
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
