Memory ICs
8k
×
8 Bit SRAM
BR6265BF-N10SL
The BR6265BF-N10SL is an 8192 word
×
8 bit CMOS static RAM. It runs on a 5V single power supply, and input can
be directed coupled with TTL. Current dissipation in the non-selected state is extremely low at 20µA (max.), and
memory information can be retained even at a low voltage of 2V, making this product ideal for battery backup opera-
tions.
Both the access and cycle timing are 100ns, facilitating timing design.
•
Applications
General-purpose
•
Featureswith an 8192
×
8 bit configuration.
1) SRAM
2) 5V single power supply voltage with ± 10% fluctua-
tion tolerance.
3) High speed access time of 100ns.
4) TTL compatible input / output.
5) Input and output use the same pin, and there are 3
output states.
6) No clock is necessary (asynchronous static circuit).
7) Input and output data are in the same phase.
8) Low power dissipation.
•
Block diagram
A8
A5
A6
A7
A12
A9
A11
I / O
0
INPUT DATA
CONTROL
I / O
7
ROW
ROW
ADDRESS
DECORDER
BUFFER
65536BIT
(128
×
512)
MEMORY CELL ARRAY
COLUMN SWITCH
COLUMN DECODER
OUTPUT DATA
CONTROL
COLUMN ADDRESS BUFFER
A0
A1
A2
A3
A4
A10
CE1
CE2
OE
WE
CONTROL
BUFFER
1
Memory ICs
BR6265BF-N10SL
•
Absolute maximum ratings (Ta = 25°C)
Parameter
Power supply voltage
Power dissipation
Operating temperature
Storage temperature
I / O voltage
Symbol
V
CC
Pd
Topr
Tstg
V
I
Limits
– 0.5
∗
1
~ + 7.0
850
∗
2
0 ~ 70
– 55 ~ + 125
– 0.5 ~ V
CC
+ 0.5
Unit
V
mW
°C
°C
V
∗
1 At pulse width of 50 ns : – 3.0V (min.)
∗
2 Reduced by 8.5mW for each increase in Ta of 1°C over 25°C.
•
Recommended operating conditions (Ta = 25°C)
Parameter
Power supply voltage
Input high level voltage
Input low level voltage
Ambient temperature
Symbol
V
CC
V
IH
V
IL
Ta
Min.
4.5
2.2
– 0.3
0
Typ.
5.0
—
—
—
Max.
5.5
V
CC
+ 0.5
0.8
70
Unit
V
V
V
°C
•
Pin descriptions
Pin No.
1
2 ~ 10, 21,
23 ~ 25
11 ~ 13,
15 ~ 19
20
26
22
27
28
14
Pin name
NC
A0 ~ A12
I / O0 ~ I / O7
CE1
CE2
OE
WE
V
CC
V
SS
Internal chip and not connected
8192-byte memory address input
8-bit data I / O
Chip enable control input
Chip enable control input
Output enable control input
Write enable control input
5V
±
10%power supply
Reference voltage for all input / output, 0V
Function
2
Memory ICs
BR6265BF-N10SL
CC
•
Electrical characteristics (unless otherwise noted, Ta = 0 to 70°C, V
Parameter
Input low level voltage
Input high level voltage
Output low level voltage
Output high level voltage
Input leakage current
Output leakage current
Symbol
V
IL
V
IH
V
OL
V
OH
I
LI
I
LO
I
CCA1
Average operating current
I
CCA2
I
SB
Standby current
I
SB1
I
SB2
—
—
—
—
—
—
—
—
10
3
20
20
mA
mA
µA
µA
Min.
– 0.3
∗
1
2.2
0
2.4
V
CC
×
0.8
—
—
—
Typ.
—
—
—
—
—
—
—
—
Max.
0.8
V
CC
+ 0.5
0.4
V
CC
V
CC
±
1
±
1
40
Unit
V
V
V
V
V
µA
µA
mA
= 5V ± 10%)
Conditions
—
—
Measurement
circuit
—
—
Fig.1
Fig.2
—
Fig.3
Fig.4
Fig.5
Fig.5
—
0.2V
Fig.6
—
I
OL
= 2.1mA
I
OH
= – 1.0mA
I
OH
= – 0.1mA
V
IN
= 0 ~ V
CC
V
OUT
= 0 ~ V
CC
CE1 = V
IL
, CE2 = V
IH
, I / O: OPEN
Minimum cycle time
CE1 = V
IL
, CE2 = V
IH
, I / O: OPEN
f = 1MHz
CE1 = V
IH
or CE2 = V
IL
CE1
CE2
CE2
V
CC
– 0.2V,
V
CC
– 0.2V or CE2
0.2V
∗
1 At input voltage pulse width of 50 ns or less : – 3.0V
3
Memory ICs
BR6265BF-N10SL
•
Measurement circuits
V
CC
V
CC
V
CC
V
CC
I / O0 ~ I / O7
V
SS
V
SS
V
V
OL
V
V
OH
2.1mA
I / O0 ~ I / O7
1.0mA
Data sets all output to LOW (Data 00)
Data sets all output to HIGH (Data FF)
Fig. 1 Output low level voltage measurement circuit
Fig. 2 Output high level voltage measurement circuit
V
CC
V
CC
V
CC
I
L1
A
V
CC
A0 ~ A12
CE1, CE2
V
SS
V
CC
OE
I / O0 ~ I / O7
V
SS
I
LO
A
V
IN
=
0 ~ V
CC
V
OUT
=
0 ~ V
CC
Fig. 3 Input leakage measurement circuit
Fig. 4 Output leakage current measurement circuit
V
CC
V
CC
V
IH
A
I
CCA1
,
I
CCA2
V
IH
A
I
SB
,
1
WE
CE2
CE1
OE
V
CC
I / O0 ~ I / O7
SW
OPEN
q
V
CC
V
IL
or V
IH
(Min. cycle)
CE1
CE2
I / O0 ~ I / O7
A0 ~ A12
V
SS
OPEN
V
CC
or GND
A0 ~ A12
V
SS
w
V
IL
or V
IH
(1MHz cycle)
V
IL
q
: Average operating current ICCA1
w
: Average operating current ICCA2
Fig. 5 Current dissipation measurement circuit
Fig. 6 Standby current measurement circuit
4
Memory ICs
BR6265BF-N10SL
•
Operating modes
Control pin
OE
X
X
H
L
X
CE1
H
X
L
L
L
CE2
X
L
H
H
H
WE
X
X
H
H
L
Mode
Wait state
Wait state
Output disabled
Read
Write
I/O
High impedance
High impedance
High impedance
Data output
Data output
Power dissipation
Standby state
Standby state
Operating state
Operating state
Operating state
X : Either V
IL
or V
IH
to
•
AC test conditions: (Ta = 02.4V70°C, V
Input pulse level
0.8 to
CC
= 5V ± 10%)
Input rise / fall time : 5ns
I / O timing level
: 1.5V
Output load
: 1 TTL gate and CL = 100pF
•
Read cycle
Parameter
Read cycle time
Address access time
CE1 access time
CE2 access time
OE access time
Output hold time
CE1 output set time
CE2 output set time
OE output reset time
CE1 deselect output floating
CE2 deselect output floating
OE
disable output floating
Symbol
t
RC
t
AA
t
CO1
t
CO2
t
OE
t
OH
t
LZ1
t
LZ2
t
OLZ
t
HZ1
t
HZ2
t
OHZ
Min.
100
—
—
—
—
10
10
10
5
—
—
—
Max.
—
100
100
100
40
—
—
—
—
35
35
35
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
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