SN54HC4020, SN74HC4020
14-BIT ASYNCHRONOUS BINARY COUNTERS
SCLS158C – DECEMBER 1982 – REVISED FEBRUARY 2000
D
Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW), and
Ceramic Flat (W) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) DIPs
SN54HC4020 . . . J OR W PACKAGE
SN74HC4020 . . . D, DB, N, OR PW PACKAGE
(TOP VIEW)
description
These devices are 14-stage binary ripple-carry
counters that advance on the negative-going
edge of the clock pulse. The counters are reset to
zero (all outputs low) independently of the clock
(CLK) input when the clear (CLR) input goes high.
The SN54HC4020 is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74HC4020 is characterized for
operation from –40°C to 85°C.
Q
L
Q
M
Q
N
Q
F
Q
E
Q
G
Q
D
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
Q
K
Q
J
Q
H
Q
I
CLR
CLK
Q
A
SN54HC4020 . . . FK PACKAGE
(TOP VIEW)
logic symbol
†
RCTR14
0
3
4
11
9
7
5
4
CLR
CT=0
CT
6
13
CLK
10
12
14
15
1
2
13
3
QA
QD
QE
QF
QG
QH
QI
QJ
QK
QL
QM
QN
Q
N
Q
F
NC
Q
E
Q
G
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
NC
V
CC
Q
K
Q
J
Q
H
NC
Q
I
CLR
NC – No internal connection
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
Pin numbers shown are for the D, DB, J, N,
PW, and W packages.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
©
2000, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
Q
D
GND
NC
Q
A
CLK
Q
M
Q
L
1
SN54HC4020, SN74HC4020
14-BIT ASYNCHRONOUS BINARY COUNTERS
SCLS158C – DECEMBER 1982 – REVISED FEBRUARY 2000
logic diagram (positive logic)
CLR
11
R
CLK
10
T
R
T
R
T
R
T
R
T
R
T
9
QA
7
QD
5
QE
4
QF
R
T
R
T
R
T
R
T
R
T
R
T
R
T
R
T
6
QG
13
QH
12
QI
14
QJ
15
QK
1
QL
2
QM
3
QN
Pin numbers shown are for the D, DB, J, N, PW, and W packages.
absolute maximum ratings over operating free-air temperature range
†
Supply voltage range, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±20
mA
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±20
mA
Continuous output current, I
O
(V
O
= 0 to V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±25
mA
Continuous current through V
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±50
mA
Package thermal impedance,
θ
JA
(see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
2
POST OFFICE BOX 655303
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DALLAS, TEXAS 75265
SN54HC4020, SN74HC4020
14-BIT ASYNCHRONOUS BINARY COUNTERS
SCLS158C – DECEMBER 1982 – REVISED FEBRUARY 2000
recommended operating conditions (see Note 3)
SN54HC4020
MIN
VCC
VIH
Supply voltage
High-level input voltage
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
VCC = 2 V
VIL
VI
VO
tt
Low-level input voltage
Input voltage
Output voltage
Input transition (rise and fall) time
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
VCC = 4.5 V
VCC = 6 V
2
1.5
3.15
4.2
0
0
0
0
0
0
0
0
0.5
1.35
1.8
VCC
VCC
1000
500
400
NOM
5
MAX
6
SN74HC4020
MIN
2
1.5
3.15
4.2
0
0
0
0
0
0
0
0
0.5
1.35
1.8
VCC
VCC
1000
500
400
ns
V
V
V
V
NOM
5
MAX
6
UNIT
V
TA
Operating free-air temperature
–55
125
–40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs,
literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
2V
IOH = –20
µA
VOH
VI = VIH or VIL
IOH = –4 mA
IOH = –5.2 mA
IOL = 20
µA
VOL
VI = VIH or VIL
IOL = 4 mA
IOL = 5.2 mA
II
ICC
Ci
VI = VCC or 0
VI = VCC or 0,
IO = 0
4.5 V
6V
4.5 V
6V
2V
4.5 V
6V
4.5 V
6V
6V
6V
2 V to 6 V
3
TA = 25°C
MIN
TYP
MAX
1.9
4.4
5.9
3.98
5.48
1.998
4.499
5.999
4.3
5.8
0.002
0.001
0.001
0.17
0.15
±0.1
0.1
0.1
0.1
0.26
0.26
±100
8
10
SN54HC4020
MIN
1.9
4.4
5.9
3.7
5.2
0.1
0.1
0.1
0.4
0.4
±1000
160
10
MAX
SN74HC4020
MIN
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
0.33
0.33
±1000
80
10
nA
µA
pF
V
V
MAX
UNIT
POST OFFICE BOX 655303
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3
SN54HC4020, SN74HC4020
14-BIT ASYNCHRONOUS BINARY COUNTERS
SCLS158C – DECEMBER 1982 – REVISED FEBRUARY 2000
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
VCC
2V
fclock
Clock frequency
4.5 V
6V
2V
CLK high or low
tw
Pulse duration
CLR high
4.5 V
6V
2V
4.5 V
6V
2V
tsu
Setup time, CLR inactive before CLK↓
↓
4.5 V
6V
TA = 25°C
MIN
MAX
0
0
0
90
18
15
70
14
12
60
12
10
5.5
28
33
SN54HC4020
MIN
0
0
0
135
27
23
105
21
18
90
18
15
MAX
3.7
19
22
SN74HC4020
MIN
0
0
0
115
23
20
90
18
25
75
15
13
ns
ns
MAX
4.3
22
25
MHz
UNIT
switching characteristics over recommended operating free-air temperature range, C
L
= 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
2V
fmax
4.5 V
6V
2V
tpd
CLK
QA
4.5 V
6V
2V
tPHL
CLR
Any
4.5 V
6V
2V
tt
Any
4.5 V
6V
TA = 25°C
MIN
TYP
MAX
5.5
28
33
10
45
53
62
16
12
63
17
13
28
8
6
150
30
26
140
28
24
75
15
13
SN54HC4020
MIN
3.7
19
22
225
45
38
210
42
36
110
22
19
MAX
SN74HC4020
MIN
4.3
22
25
190
38
32
175
35
30
95
19
16
ns
ns
ns
MHz
MAX
UNIT
operating characteristics, T
A
= 25°C
PARAMETER
Cpd
Power dissipation capacitance
TEST CONDITIONS
No load
TYP
88
UNIT
pF
4
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
SN54HC4020, SN74HC4020
14-BIT ASYNCHRONOUS BINARY COUNTERS
SCLS158C – DECEMBER 1982 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
Test
Point
CL = 50 pF
(see Note A)
LOAD CIRCUIT
VCC
50%
tPLH
In-Phase
Output
50%
10%
tPHL
Out-of-Phase
Output
90%
50%
10%
tf
90%
tr
tPLH
50%
10%
90%
tr
50%
0V
tPHL
90%
VOH
50%
10%
VOL
tf
VOH
VOL
Low-Level
Pulse
50%
Data
Input
50%
10%
Reference
Input
tsu
90%
90%
VCC
50%
10% 0 V
tf
50%
VCC
0V
tr
Input
VOLTAGE WAVEFORMS
SETUP AND INPUT RISE AND FALL TIMES
High-Level
Pulse
VCC
50%
tw
VCC
50%
0V
VOLTAGE WAVEFORMS
PULSE DURATIONS
50%
0V
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
NOTES: A. CL includes probe and test-fixture capacitance.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR
≤
1 MHz, ZO = 50
Ω,
tr = 6 ns, tf = 6 ns.
C. For clock inputs, fmax is measured when the input duty cycle is 50%.
D. The outputs are measured one at a time with one input transition per measurement.
E. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
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5
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