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SN74CBTLVR16292
LOW VOLTAGE 12 BIT 1 OF 2 FET MULTIPLEXER/DEMULTIPLEXER
WITH INTERNAL PULLDOWN RESISTORS
SCDS056H − MARCH 1998 − REVISED OCTOBER 2003
D
Member of the Texas Instruments
D
D
D
D
D
D
D
Widebus Family
Rail-to-Rail Switching on Data I/O Ports
I
off
Supports Partial-Power-Down Mode
Operation
Make-Before-Break Feature
Internal 500-Ω Pulldown Resistors to
Ground
Input/Output Ports Have Equivalent 25-Ω
Series Resistors, So No External Resistors
Are Required
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
description/ordering information
The SN74CBTLVR16292 is a 12-bit 1-of-2
high-speed FET multiplexer/demultiplexer. The
low on-state resistance of the switch allows
connections to be made with minimal propagation
delay.
When the select (S) input is low, port A is
connected to port B1, and R
INT
is connected to
port B2. When S is high, port A is connected to
port B2, and R
INT
is connected to port B1.
The input/output ports include equivalent 25-Ω
series resistors to reduce overshoot and
undershoot.
This
device
is
fully
specified
for
partial-power-down applications using I
off
. The I
off
feature ensures that damaging current will not
backflow through the device when it is powered
down. The device has isolation during power off.
S
1A
NC
2A
NC
3A
NC
GND
4A
NC
5A
NC
6A
NC
7A
NC
V
CC
8A
GND
NC
9A
NC
10A
NC
11A
NC
12A
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
NC
NC
1B1
1B2
2B1
2B2
3B1
GND
3B2
4B1
4B2
5B1
5B2
6B1
6B2
7B1
7B2
8B1
GND
8B2
9B1
9B2
10B1
10B2
11B1
11B2
12B1
12B2
NC − No internal connection
ORDERING INFORMATION
TA
PACKAGE†
Tube
SSOP − DL
−40°C to 85°C
TSSOP − DGG
TVSOP − DGV
Tape and reel
Tape and reel
Tape and reel
ORDERABLE
PART NUMBER
SN74CBTLVR16292L
SN74CBTLVR16292LR
SN74CBTLVR16292GR
SN74CBTLVR16292VR
CBTLVR16292
CBTLVR16292
CE292
TOP-SIDE
MARKING
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
2003, Texas Instruments Incorporated
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
1
SCDS056H − MARCH 1998 − REVISED OCTOBER 2003
SN74CBTLVR16292
LOW VOLTAGE 12 BIT 1 OF 2 FET MULTIPLEXER/DEMULTIPLEXER
WITH INTERNAL PULLDOWN RESISTORS
FUNCTION TABLE
INPUT
S
L
H
FUNCTION
A port = B1 port
RINT = B2 port
A port = B2 port
RINT = B1 port
logic diagram (positive logic)
2
1A
SW
54
1B1
RINT
RINT
53
SW
1B2
27
12A
SW
RINT
30
12B1
RINT
29
SW
12B2
1
S
2
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DALLAS, TEXAS 75265
SN74CBTLVR16292
LOW VOLTAGE 12 BIT 1 OF 2 FET MULTIPLEXER/DEMULTIPLEXER
WITH INTERNAL PULLDOWN RESISTORS
SCDS056H − MARCH 1998 − REVISED OCTOBER 2003
simplified schematic, each FET switch
A
B
(OE)
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Input voltage range, V
I
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, I
IK
(V
I
< 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Package thermal impedance,
θ
JA
(see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48°C/W
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56°C/W
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
MIN
VCC
VIH
VIL
Supply voltage
High-level control input voltage
Low-level control input voltage
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
2.3
1.7
2
0.7
0.8
V
V
MAX
3.6
UNIT
V
TA
Operating free-air temperature
−40
85
°C
NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs,
literature number SCBA004.
POST OFFICE BOX 655303
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DALLAS, TEXAS 75265
3
SCDS056H − MARCH 1998 − REVISED OCTOBER 2003
SN74CBTLVR16292
LOW VOLTAGE 12 BIT 1 OF 2 FET MULTIPLEXER/DEMULTIPLEXER
WITH INTERNAL PULLDOWN RESISTORS
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
II
Ioff
ICC
∆I
CC‡
Ci
Cio
Control input
Control input
A or B port
VCC = 3 V,
VCC = 3.6 V,
VCC = 0,
VCC = 3.6 V,
VCC = 3.6 V,
VI = 3.3 V or 0
VO = 3.3 V or 0
VCC = 2.3 V,
TYP at VCC = 2.5 V
ron§
VCC = 3 V
VI = 0
VI = 1.7 V,
VI = 0
II = 64 mA
II = 24 mA
II = 15 mA
II = 64 mA
II = 24 mA
TEST CONDITIONS
II = −18 mA
VI = VCC or GND
VI or VO = 0 to 3.6 V
IO = 0,
VI = VCC or GND
One input at 3 V,
Other inputs at VCC or GND
3.5
23
30
30
36
30
30
47
47
80
42
42
Ω
MIN
TYP†
MAX
−1.2
±1
10
10
300
UNIT
V
µA
µA
µA
µA
pF
pF
VI = 2.4 V,
II = 15 mA
32
47
† All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C.
‡ This is the increase in supply current for each input that is at the specified voltage level, rather than VCC or GND.
§ Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by
the lower of the voltages of the two (A or B) terminals.
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
PARAMETER
tpd¶
tpd#
ten
tdis
FROM
(INPUT)
A or B
S
S
S
TO
(OUTPUT)
B or A
A
B
B
3.2
1
1
VCC = 2.5 V
±
0.2 V
MIN
MAX
0.15
8.5
6.5
5.3
3.2
1
1
VCC = 3.3 V
±
0.3 V
MIN
MAX
0.25
8
5.8
4.6
ns
ns
ns
ns
UNIT
¶ The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when
driven by an ideal voltage source (zero output impedance).
# This propagation delay was measured by observing the change of voltage on the A output introduced by static levels equal to 3-V or 0 for
3.3 V
±
0.3 V or VCC or 0 for 2.5 V
±
0.2 V on B1 and B2 to achieve the desired transition.
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
PARAMETER
DESCRIPTION
VCC = 2.5 V
±
0.2 V
MIN
MAX
VCC = 3.3 V
±
0.3 V
MIN
MAX
ns
UNIT
tmbb||
Make-before-break time
0
2
0
2
|| The make-before-break time is the time interval between make and break, during the transition from one selected port to the other.
4
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