Preliminary
KM68FS8100 Family
Document Title
1M x8 bit Super Low Power and Low Voltage Full CMOS Static RAM
CMOS SRAM
Revision History
Revision No. History
0.0
Initial draft
Draft Date
August 25, 1999
Remark
Preliminary
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to yourquestions about device. If you have any questions, please contact the SAMSUNG branch offices.
1
Revision 0.0
August 1999
Preliminary
KM68FS8100 Family
FEATURES
•
Process Technology: Full CMOS
•
Organization: 1M x8
•
Power Supply Voltage: 2.3~2.7V
•
Low Data Retention Voltage: 1.5V(Min)
•
Three state output and TTL Compatible
•
Package Type: 48-FBGA-8.00x12.00
CMOS SRAM
GENERAL DESCRIPTION
The KM68FS8100 families are fabricated by SAMSUNG′s
advanced full CMOS process technology. The families support
industrial operating temperature ranges and have chip scale
package for user flexibility of system design. The families also
support low data retention voltage for battery back-up operation
with low data retention current.
1M x 8 bit Super Low Power and Low Voltage Full CMOS Static RAM
PRO
DUCT FAMILY
Power Dissipation
Product Family
KM68FS8100I
Operating Temperature
Industrial(-40~85°C)
Vcc Range
2.3~2.7V
Speed
70*/85ns
Standby
(I
SB1
, Typ.)
0.5µA
Operating
(I
CC1
, Max)
3mA
PKG Type
48-FBGA-8.00x12.00
1. The parameter is measured with 30pF test load.
PIN DESCRIPTION
1
2
3
4
5
6
FUNCTIONAL BLOCK DIAGRAM
Clk gen.
Precharge circuit.
A
DNU
OE
A0
A1
A2
CS2
Vcc
Vss
B
DNU
DNU
A3
A4
CS1
DNU
Row
Addresses
Row
select
Memory array
2048 rows
256×8 columns
C
I/O1
DNU
A5
A6
DNU
I/O5
D
Vss
I/O2
A17
A7
I/O6
Vcc
E
Vcc
I/O3
V
CC
A16
I/O7
Vss
I/O
1
~I/O
8
Data
cont
I/O Circuit
Column select
F
I/O4
DNU
A14
A15
DNU
I/O8
Data
cont
G
DNU
DNU
A12
A13
WE
DNU
Column Addresses
H
A18
A8
A9
A10
A11
A19
CS1
CS2
OE
WE
48-FBGA: Top View (Ball Down)
Control Logic
Name
CS
1
, CS
2
OE
WE
Function
Chip Select Inputs
Output Enable Input
Write Enable Input
Name
Function
A
0
~A
19
Address Inputs
Vcc
Vss
DNU
Power
Ground
Do Not Use
I/O
1
~I/O
16
Data Inputs/Outputs
SAMSUNG ELECTRONICS CO., LTD.
reserves the right to change products and specifications without notice.
2
Revision 0.0
August 1999
Preliminary
KM68FS8100 Family
PRODUCT LIST
Industrial Temperature Products(-40~85°C)
Part Name
KM68FS8100FI-7
KM68FS8100FI-8
Function
48-FBGA, 70ns, 2.5V
48-FBGA, 85ns, 2.5V
CMOS SRAM
FUNCTIONAL DESCRIPTION
CS
1
H
X
1)
L
L
L
CS
2
X
1)
L
H
H
H
OE
X
1)
X
1)
H
L
X
1)
WE
X
1)
X
1)
H
H
L
I/O
1~8
High-Z
High-Z
High-Z
Dout
Din
Mode
Deselected
Deselected
Output Disabled
Read
Write
Power
Standby
Standby
Active
Active
Active
1. X means don′t care. (Must be low or high state)
ABSOLUTE MAXIMUM RATINGS
1)
Item
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
Storage temperature
Operating Temperature
Symbol
V
IN
,V
OUT
V
CC
P
D
T
STG
T
A
Ratings
-0.2 to 3.0
-0.2 to 3.6
1.0
-55 to 150
-40 to 85
Unit
V
V
W
°C
°C
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
3
Revision 0.0
August 1999
Preliminary
KM68FS8100 Family
RECOMMENDED DC OPERATING CONDITIONS
1)
Item
Supply voltage
Ground
Input high voltage
Input low voltage
Symbol
Vcc
Vss
V
IH
V
IL
Min
2.3
0
2.2
-0.2
3)
Typ
2.5
0
-
-
CMOS SRAM
Max
2.7
0
Vcc+0.2
2)
0.4
Unit
V
V
V
V
Note:
1. T
A
=-40 to 85°C, otherwise specified
2. Overshoot: V
CC
+1.0V in case of pulse width
≤20ns.
3. Undershoot: -1.0V in case of pulse width
≤20ns.
4. Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE
1)
(f=1MHz, T
A
=25°C)
Item
Input capacitance
Input/Output capacitance
1. Capacitance is sampled, not 100% tested
Symbol
C
IN
C
IO
Test Condition
V
IN
=0V
V
IO
=0V
Min
-
-
Max
8
10
Unit
pF
pF
DC AND OPERATING CHARACTERISTICS
Item
Input leakage current
Output leakage current
Operating power supply current
Symbol
I
LI
I
LO
I
CC
I
CC1
Average operating current
I
CC2
Output low voltage
Output high voltage
Standby Current(TTL)
Standby Current(CMOS)
V
OL
V
OH
I
SB
I
SB1
V
IN
=Vss to Vcc
CS
1
=V
IH,
CS
2
=V
IL
or OE=V
IH
or WE=V
IL
, V
IO
=Vss to Vcc
I
IO
=0mA, CS
1
=V
IL,
CS
2
=V
IH
, WE=V
IH
, V
IN
=V
IH
or V
IL
Cycle time=1µs, 100%duty, I
IO
=0mA, CS
1
≤0.2V,
CS
2
≥Vcc-0.2V,
V
IN
≤0.2V
or V
IN
≥VCC-0.2V
Cycle time=Min, I
IO
=0mA, 100% duty,
CS
1
=V
IL
, CS
2
=V
IH,
VIN=V
IL
or V
IH
I
OL
= 2.1mA
I
OH
= -1.0mA
CS
1
=V
IH
, CS
2
=V
IL
, Other inputs=V
IH
or V
IL
CS
1
≥Vcc-0.2V,
CS
2
≥Vcc-0.2V(CS
1
controlled) or
CS
2
≤0.2V(CS
2
controlled), Other inputs=0~Vcc
2.2
-
-
-
0.5
0.3
20
1)
Test Conditions
Min
-1
-1
-
-
-
Typ
-
-
-
-
-
Max
1
1
2
2
25
0.4
Unit
µA
µA
mA
mA
mA
V
V
mA
µA
1. Super low power product=10µA with special handling.
4
Revision 0.0
August 1999
Preliminary
KM68FS8100 Family
AC OPERATING CONDITIONS
TEST CONDITIONS
(Test Load and Input/Output Reference)
Input pulse level: 0.2 to 2.2V
Input rising and falling time: 5ns
Input and output reference voltage:1.1V
Output load(see right): C
L
=100pF+1TTL
C
L
=30pF+1TTL
CMOS SRAM
V
TM
3)
R
1
2)
C
L
1)
R
2
2)
AC CHARACTERISTICS
(Vcc=2.3~2.7V, T
A
=-40 to 85°C)
Parameter List
Symbol
Min
Read cycle time
Address access time
Chip select to output
Output enable to valid output
Read
Chip select to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
OE disable to high-Z output
Output hold from address change
Write cycle time
Chip select to end of write
Address set-up time
Address valid to end of write
Write
Write pulse width
Write recovery time
Write to output high-Z
Data to write time overlap
Data hold from write time
End write to output low-Z
t
RC
t
AA
t
CO1
, t
CO2
t
OE
t
LZ1
, t
LZ2
t
OLZ
t
HZ1
, t
HZ2
t
OHZ
t
OH
t
WC
t
CW1
, t
CW2
t
AS
t
AW
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
70
-
-
-
10
5
0
0
10
70
60
0
60
50
0
0
25
0
5
1. Including scope and jig capacitance
2. R
1
=3070Ω
,
R
2
=3150Ω
3. V
TM
=2.3V
Speed Bins
70ns
Max
-
70
70
35
-
-
25
25
-
-
-
-
-
-
-
25
-
-
-
Min
85
-
-
-
10
5
0
0
10
85
70
0
70
60
0
0
35
0
5
85ns
Max
-
85
85
40
-
-
25
25
-
-
-
-
-
-
-
25
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
DATA RETENTION CHARACTERISTICS
Item
Vcc for data retention
Data retention current
Data retention set-up time
Recovery time
Symbol
V
DR
I
DR
t
SDR
t
RDR
Test Condition
CS
1
≥Vcc-0.2V
1)
Vcc=1.5V, CS
1
≥Vcc-0.2V
1)
See data retention waveform
Min
1.5
-
0
tRC
Typ
-
0.5
-
-
Max
2.7
6
2)
-
-
Unit
V
µA
ms
1. CS
1
≥Vcc-0.2V,CS
2
≥
Vcc-0.2V(CS
1
controlled) or CS
2
≥
Vcc-0.2V(CS
2
controlled).
2. Super low power product=4µA with special handling.
5
Revision 0.0
August 1999
微控制器 MCU
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