CD4066B
CMOS QUAD BILATERAL SWITCH
SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003
D
15-V Digital or
±7.5-V
Peak-to-Peak
D
D
D
D
D
D
Switching
125-Ω Typical On-State Resistance for 15-V
Operation
Switch On-State Resistance Matched to
Within 5
Ω
Over 15-V Signal-Input Range
On-State Resistance Flat Over Full
Peak-to-Peak Signal Range
High On/Off Output-Voltage Ratio: 80 dB
Typical at f
is
= 10 kHz, R
L
= 1 kΩ
High Degree of Linearity: <0.5% Distortion
Typical at f
is
= 1 kHz, V
is
= 5 V p-p,
V
DD
− V
SS
≥
10 V, R
L
= 10 kΩ
Extremely Low Off-State Switch Leakage,
Resulting in Very Low Offset Current and
High Effective Off-State Resistance: 10 pA
Typical at V
DD
− V
SS
= 10 V, T
A
= 25°C
Extremely High Control Input Impedance
(Control Circuit Isolated From Signal
Circuit): 10
12
Ω
Typical
Low Crosstalk Between Switches: −50 dB
Typical at f
is
= 8 MHz, R
L
= 1 kΩ
D
Matched Control-Input to Signal-Output
D
D
D
D
Capacitance: Reduces Output Signal
Transients
Frequency Response, Switch On = 40 MHz
Typical
100% Tested for Quiescent Current at 20 V
5-V, 10-V, and 15-V Parametric Ratings
Meets All Requirements of JEDEC Tentative
Standard No. 13-B,
Standard Specifications
for Description of “B” Series CMOS
Devices
Applications:
− Analog Signal Switching/Multiplexing:
Signal Gating, Modulator, Squelch
Control, Demodulator, Chopper,
Commutating Switch
− Digital Signal Switching/Multiplexing
− Transmission-Gate Logic Implementation
− Analog-to-Digital and Digital-to-Analog
Conversion
− Digital Control of Frequency, Impedance,
Phase, and Analog-Signal Gain
D
D
D
E, F, M, NS, OR PW PACKAGE
(TOP VIEW)
SIG A IN/OUT
SIG A OUT/IN
SIG B OUT/IN
SIG B IN/OUT
CONTROL B
CONTROL C
V
SS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
DD
CONTROL A
CONTROL D
SIG D IN/OUT
SIG D OUT/IN
SIG C OUT/IN
SIG C IN/OUT
description/ordering information
The CD4066B is a quad bilateral switch intended for the transmission or multiplexing of analog or digital signals.
It is pin-for-pin compatible with the CD4016B, but exhibits a much lower on-state resistance. In addition, the
on-state resistance is relatively constant over the full signal-input range.
The CD4066B consists of four bilateral switches, each with independent controls. Both the p and the n devices
in a given switch are biased on or off simultaneously by the control signal. As shown in Figure 1, the well of the
n-channel device on each switch is tied to either the input (when the switch is on) or to V
SS
(when the switch
is off). This configuration eliminates the variation of the switch-transistor threshold voltage with input signal and,
thus, keeps the on-state resistance low over the full operating-signal range.
The advantages over single-channel switches include peak input-signal voltage swings equal to the full supply
voltage and more constant on-state impedance over the input-signal range. However, for sample-and-hold
applications, the CD4016B is recommended.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
2003, Texas Instruments Incorporated
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1
CD4066B
CMOS QUAD BILATERAL SWITCH
SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003
description/ordering information (continued)
ORDERING INFORMATION
TA
CDIP − F
PDIP − E
PACKAGE†
Tube of 25
Tube of 25
Tube of 50
−55°C to 125°C
SOIC − M
SOP − NS
TSSOP − PW
Reel of 2500
Reel of 250
Reel of 2000
Tube of 90
Reel of 2000
ORDERABLE
PART NUMBER
CD4066BF3A
CD4066BE
CD4066BM
CD4066BM96
CD4066BMT
CD4066BNSR
CD4066BPW
CD4066BPWR
CD4066B
CM066B
CD4066BM
TOP-SIDE
MARKING
CD4066BF3A
CD4066BE
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Switch
Control
In
Vis
p
n
p
n
Out
Vos
Control
VC†
n
VSS
VDD
VSS
† All control inputs are protected by the CMOS protection network.
NOTES: A. All p substrates are connected to VDD.
B. Normal operation control-line biasing: switch on (logic 1), VC = VDD; switch off (logic 0), VC = VSS
C. Signal-level range: VSS
≤
Vis
≤
VDD
92CS-29113
Figure 1. Schematic Diagram of One-of-Four Identical Switches and Associated Control Circuitry
2
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CD4066B
CMOS QUAD BILATERAL SWITCH
SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
†
DC supply-voltage range, V
DD
(voltages referenced to V
SS
terminal) . . . . . . . . . . . . . . . . . . . . −0.5 V to 20 V
Input voltage range, V
is
(all inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
DD
+
0.5 V
DC input current, I
IN
(any one input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±10
mA
Package thermal impedance,
θ
JA
(see Note 1): E package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
M package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
Lead temperature (during soldering):
At distance 1/16
±
1/32 inch (1,59
±
0,79 mm) from case for 10 s max . . . . . . . . . . . . . . . . . . . . . . . 265°C
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions
MIN
VDD
TA
Supply voltage
Operating free-air temperature
3
−55
MAX
18
125
UNIT
V
°C
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CD4066B
CMOS QUAD BILATERAL SWITCH
SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003
electrical characteristics
LIMITS AT INDICATED TEMPERATURES
PARAMETER
TEST CONDITIONS
VIN
(V)
0, 5
IDD
Quiescent device
current
0, 10
0, 15
0, 20
Signal Inputs (Vis) and Outputs (Vos)
VC = VDD,
RL = 10 kΩ returned
V
DD
*
V
SS
to
,
2
Vis = VSS to VDD
On-state resistance
difference between
any two switches
Total harmonic
distortion
−3-dB cutoff
frequency
(switch on)
−50-dB feedthrough
frequency (switch off)
Iis
Input/output leakage
current (switch off)
(max)
−50-dB crosstalk
frequency
5
10
15
5
RL = 10 kΩ, VC = VDD
10
15
VC = VDD = 5 V, VSS = −5 V,
Vis(p-p) = 5 V (sine wave centered on 0 V),
RL = 10 kΩ, fis = 1-kHz sine wave
VC = VDD = 5 V, VSS = −5 V, Vis(p-p) = 5 V
(sine wave centered on 0 V), RL = 1 kΩ
VC = VSS = −5 V, Vis(p-p) = 5 V
(sine wave centered on 0 V), RL = 1 kΩ
VC = 0 V, Vis = 18 V, Vos = 0 V;
and
VC = 0 V, Vis = 0 V, Vos = 18 V
VC(A) = VDD = 5 V,
VC(B) = VSS = −5 V,
Vis(A) = 5 Vp-p, 50-Ω source,
RL = 1 kΩ
RL = 200 kΩ, VC = VDD,
VSS = GND, CL = 50 pF,
Vis = 10 V
(square wave centered on 5 V),
tr, tf = 20 ns
VDD = 5 V, VC = VSS = −5 V
VDD = 5 V, VC = VSS = −5 V
VDD = 5 V, VC = VSS = −5 V
18
±0.1
±0.1
±1
±1
800
310
200
850
330
210
1200
500
300
1300
550
320
470
180
125
15
10
5
0.4
%
Ω
1050
400
240
Ω
VDD
(V)
5
10
15
20
25°C
−55°C
0.25
0.5
1
5
−40°C
0.25
0.5
1
5
85°C
7.5
15
30
150
125°C
7.5
15
30
150
TYP
0.01
0.01
0.01
0.02
MAX
0.25
0.5
1
5
µA
A
UNIT
ron
On-state resistance
(max)
∆r
on
THD
40
MHz
1
±10
−5
±0.1
MHz
µA
8
MHz
5
10
15
20
10
7
8
8
0.5
40
20
15
pF
pF
pF
ns
tpd
Propagation delay
(signal input to
signal output)
Input capacitance
Output capacitance
Feedthrough
Cis
Cos
Cios
4
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CD4066B
CMOS QUAD BILATERAL SWITCH
SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003
electrical characteristics (continued)
LIMITS AT INDICATED TEMPERATURES
CHARACTERISTIC
Control (VC)
VILC
Control input,
low voltage (max)
|Iis| < 10
µA,
Vis = VSS, VOS = VDD, and
Vis = VDD, VOS = VSS
5
10
15
5
VIHC
Control input,
high voltage
Input current (max)
Crosstalk (control input
to signal output)
Turn-on and turn-off
propagation delay
See Figure 6
Vis
≤
VDD, VDD − VSS = 18 V,
VCC
≤
VDD − VSS
VC = 10 V (square wave),
tr, tf = 20 ns, RL = 10 kΩ
VIN = VDD, tr, tf = 20 ns,
CL = 50 pF, RL = 1 kΩ
Vis = VDD, VSS = GND,
RL = 1 kΩ to GND, CL = 50 pF,
VC = 10 V (square wave
centered on 5 V), tr, tf = 20 ns,
Vos = 1/2 Vos at 1 kHz
10
15
IIN
18
10
5
10
15
5
10
15
±0.1
±0.1
1
2
2
1
2
2
1
2
2
3.5 (MIN)
7 (MIN)
11 (MIN)
±1
±1
±10
−5
50
35
20
15
6
9
9.5
5
7.5
pF
MHz
70
40
30
ns
±0.1
µA
mV
V
1
2
2
1
2
2
V
TEST CONDITIONS
VDD
(V)
25°C
−55°C
−40°C
85°C
125°C
TYP
MAX
UNIT
Maximum control input
repetition rate
CI
Input capacitance
switching characteristics
SWITCH INPUT
VDD
(V)
5
5
10
10
15
15
Vis
(V)
0
5
0
10
0
15
Iis (mA)
−55°C
0.64
−0.64
1.6
−1.6
4.2
−4.2
−40°C
0.61
−0.61
1.5
−1.5
4
−4
25°C
0.51
−0.51
1.3
−1.3
3.4
−3.4
85°C
0.42
−0.42
1.1
−1.1
2.8
−2.8
125°C
0.36
−0.36
0.9
−0.9
2.4
−2.4
13.5
9.5
1.5
4.6
0.5
SWITCH
OUTPUT, Vos
(V)
MIN
MAX
0.4
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