128MB, 256MB, 512MB (x64)
200-PIN DDR SODIMM
SMALL-OUTLINE
DDR SDRAM MODULE
Features
• 200-pin, small-outline, dual in-line memory
module (SODIMM)
• Fast data transfer rates PC1600, PC2100, or PC2700
• Utilizes 200 MT/s, 266 MT/s, and 333MT/s DDR
SDRAM components
• 128MB (16 Meg x 64), 256MB (32 Meg x 64), or
512MB (64 Meg x 64)
• V
DD
= V
DD
Q = +2.5V
• V
DDSPD
= +2.3V to +3.6V
• 2.5V I/O (SSTL_2 compatible)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• Internal, pipelined double data rate (DDR)
architecture; two data accesses per clock cycle
• Bidirectional data strobe (DQS) transmitted/received
with data—i.e., source-synchronous data capture
• Differential clock inputs CK and CK#
• Four internal device banks for concurrent operation
• Programmable burst lengths: 2, 4, or 8
• Auto precharge option
• Serial Presence Detect (SPD) with EEPROM
• Programmable READ CAS latency
• Auto Refresh and Self Refresh Modes
• 15.6µs (128MB), 7.8125µs (256MB and 512MB)
maximum average periodic refresh interval
• Gold edge contacts
MT8VDDT1664HD – 128MB
MT8VDDT3264HD – 256MB
MT8VDDT6464HD – 512MB
For the latest data sheet, please refer to the Micron
â
Web
site:
www.micron.com/moduleds
Figure 1: 200-Pin SODIMM (MO-224)
OPTIONS
• Package
200-pin SODIMM (Standard)
200-pin SODIMM (Lead-free)
1
• Frequency/CAS Latency
2
6ns/166 MHz (333MT/s) CL=2.5
7.5ns/133 MHz (266 MT/s) CL = 2
7.5ns/133 MHz (266 MT/s) CL = 2
7.5ns/133 MHz (266 MT/s) CL = 2.5
10ns/100 MHz (200 MT/s) CL = 2
NOTE:
MARKING
G
Y
-335
-262
-26A
-265
-202
1. Consult with factory for availability of lead-free
products.
2. CL = CAS (READ) Latency
Table 1:
Address Table
128MB
256MB
8K
8K (A0–A12)
4 (BA0, BA1)
16 Meg x 16
512 (A0–A8)
2 (S0#, S1#)
512MB
8K
8K (A0–A12)
4 (BA0, BA1)
32 Meg x 16
1K (A0–A9)
2 (S0#, S1#)
4K
4K (A0–A11)
4 (BA0, BA1)
8 Meg x 16
512 (A0–A8)
2 (S0#, S1#)
Refresh Count
Row Addressing
Device Bank Addressing
Device Configuration
Column Addressing
Module Rank Addressing
09005aef806e1d28
DD8C16_32_64x64HDG_B.fm - Rev. B 10/03 EN
1
©2003 Micron Technology, Inc. All rights reserved.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
128MB, 256MB, 512MB (x64)
200-PIN DDR SODIMM
Table 2:
Part Numbers and Timing Parameters
MODULE
DENSITY
128MB
128MB
128MB
128MB
128MB
128MB
128MB
128MB
128MB
128MB
256MB
256MB
256MB
256MB
256MB
256MB
256MB
256MB
256MB
256MB
512MB
512MB
512MB
512MB
512MB
512MB
512MB
512MB
512MB
512MB
CONFIGURATION
16 Meg x 64
16 Meg x 64
16 Meg x 64
16 Meg x 64
16 Meg x 64
16 Meg x 64
16 Meg x 64
16 Meg x 64
16 Meg x 64
16 Meg x 64
32 Meg x 64
32 Meg x 64
32 Meg x 64
32 Meg x 64
32 Meg x 64
32 Meg x 64
32 Meg x 64
32 Meg x 64
32 Meg x 64
32 Meg x 64
64 Meg x 64
64 Meg x 64
64 Meg x 64
64 Meg x 64
64 Meg x 64
64 Meg x 64
64 Meg x 64
64 Meg x 64
64 Meg x 64
64 Meg x 64
MODULE
BANDWIDTH
2.7 GB/s
2.7 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
1.6 GB/s
1.6 GB/s
2.7 GB/s
2.7 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
1.6 GB/s
1.6 GB/s
2.7 GB/s
2.7 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
1.6 GB/s
1.6 GB/s
MEMORY CLOCK/
DATA BIT RATE
6ns/333 MT/s
6ns/333 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
10ns/200 MT/s
10ns/200 MT/s
6ns/333 MT/s
6ns/333 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
10ns/200 MT/s
10ns/200 MT/s
6ns/333 MT/s
6ns/333 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
10ns/200 MT/s
10ns/200 MT/s
LATENCY
(CL -
T
RCD -
T
RP)
2.5-3-3
2.5-3-3
2-2-2
2-2-2
2-3-3
2-3-3
2.5-3-3
2.5-3-3
2-2-2
2-2-2
2.5-3-3
2.5-3-3
2-2-2
2-2-2
2-3-3
2-3-3
2.5-3-3
2.5-3-3
2-2-2
2-2-2
2.5-3-3
2.5-3-3
2-2-2
2-2-2
2-3-3
2-3-3
2.5-3-3
2.5-3-3
2-2-2
2-2-2
PART NUMBER
MT8VDDT1664HDG-335__
MT8VDDT1664HDY-335__
MT8VDDT1664HDG-262__
MT8VDDT1664HDY-262__
MT8VDDT1664HDG-26A__
MT8VDDT1664HDY-26A__
MT8VDDT1664HDG-265__
MT8VDDT1664HDY-265__
MT8VDDT1664HDG-202__
MT8VDDT1664HDY-202__
MT8VDDT3264HDG-335__
MT8VDDT3264HDY-335__
MT8VDDT3264HDG-262__
MT8VDDT3264HDY-262__
MT8VDDT3264HDG-26A__
MT8VDDT3264HDY-26A__
MT8VDDT3264HDG-265__
MT8VDDT3264HDY-265__
MT8VDDT3264HDG-202__
MT8VDDT3264HDY-202__
MT8VDDT6464HDG-335__
MT8VDDT6464HDY-335__
MT8VDDT6464HDG-262__
MT8VDDT6464HDY-262__
MT8VDDT6464HDG-26A__
MT8VDDT6464HDY-26A__
MT8VDDT6464HDG-265__
MT8VDDT6464HDY-265__
MT8VDDT6464HDG-202__
MT8VDDT6464HDY-202__
NOTE:
All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for
current revision codes. Example: MT8VDDT3264HDG-265A1.
09005aef806e1d28
DD8C16_32_64x64HDG_B.fm - Rev. B 10/03 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
128MB, 256MB, 512MB (x64)
200-PIN DDR SODIMM
Table 3:
Pin Assignment
(200-Pin SODIMM Front)
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
V
SS
DQ19
DQ24
V
DD
DQ25
DQS3
V
SS
DQ26
DQ27
V
DD
DNU
DNU
V
SS
DNU
DNU
V
DD
DNU
NC
V
SS
CK2
CK2#
V
DD
CKE1
NC
NC/A12
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
A9
V
SS
A7
A5
A3
A1
V
DD
A10
BA0
WE#
S0#
NC
V
SS
DQ32
DQ33
V
DD
DQS4
DQ34
V
SS
DQ35
DQ40
V
DD
DQ41
DQS5
V
SS
151 DQ42
153 DQ43
155
V
DD
157
V
DD
159
V
SS
161
V
SS
163 DQ48
165 DQ49
167
V
DD
169 DQS6
171 DQ50
173
V
SS
175 DQ51
177 DQ56
179
V
DD
181 DQ57
183 DQS7
185
V
SS
187 DQ58
189 DQ59
191
V
DD
193
SDA
195
SCL
197 V
DDSPD
199
NC
Table 4:
Pin Assignment
(200-Pin SODIMM BACK)
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
V
SS
DQ23
DQ28
V
DD
DQ29
DM3
V
SS
DQ30
DQ31
V
DD
DNU
DNU
V
SS
DNU
DNU
V
DD
DNU
NC
V
SS
V
SS
V
DD
V
DD
CKE0
NC
A11
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
A8
V
SS
A6
A4
A2
A0
V
DD
BA1
RAS#
CAS#
S1#
NC
V
SS
DQ36
DQ37
V
DD
DM4
DQ38
V
SS
DQ39
DQ44
V
DD
DQ45
DM5
V
SS
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
DQ46
DQ47
V
DD
CK1#
CK1
V
SS
DQ52
DQ53
V
DD
DM6
DQ54
V
SS
DQ55
DQ60
V
DD
DQ61
DM7
V
SS
DQ62
DQ63
V
DD
SA0
SA1
SA2
NC
PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
NOTE:
PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
V
REF
V
SS
DQ4
DQ5
V
DD
DM0
DQ6
V
SS
DQ7
DQ12
V
DD
DQ13
DM1
V
SS
DQ14
DQ15
V
DD
V
DD
V
SS
V
SS
DQ20
DQ21
V
DD
DM2
DQ22
V
REF
V
SS
DQ0
DQ1
V
DD
DQS0
DQ2
V
SS
DQ3
DQ8
V
DD
DQ9
DQS1
V
SS
DQ10
DQ11
V
DD
CK0
CK0#
V
SS
DQ16
DQ17
V
DD
DQS2
DQ18
Pin 99 is No Connect for 128MB, A12 for 256MB and 512MB.
Figure 2: Module Layout
Front View
U9
Back View
U1
U2
U3
U4
U8
U7
U6
U5
PIN 1
(all odd pins)
PIN 199
PIN 200
(all even pins)
PIN 2
09005aef806e1d28
DD8C16_32_64x64HDG_B.fm - Rev. B 10/03 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
128MB, 256MB, 512MB (x64)
200-PIN DDR SODIMM
Table 5:
Pin Descriptions
SYMBOL
WE#, CAS#, RAS#
TYPE
DESCRIPTION
Pin numbers may not correlate with symbols. Refer to Pin Assignment Tables for pin number and symbol information
PIN NUMBERS
118, 119, 120
Input Command Inputs: RAS#, CAS#, and WE# (along with S#)
define the command being entered.
35, 37, 89, 91, 158, 160
CK0, CK0#,
Input Clock: CK, CK# are differential clock inputs. All address and
CK1, CK1#,
control input signals are sampled on the crossing of the
CK2, CK2#
positive edge of CK,and negative edge of CK#. Output data
(DQs and DQS) is referenced to the crossings of CK and CK#.
95, 96
CKE0, CKE1
Input Clock Enable: CKE HIGH activates and CKE LOW deactivates
the internal clock, input buffers and output drivers. Taking
CKE LOW provides PRECHARGE POWER-DOWN and SELF
REFRESH operations (all device banks idle), or ACTIVE POWER-
DOWN (row ACTIVE in any device bank). CKE is synchronous
for POWER-DOWN entry and exit, and for SELF REFRESH
entry. CKE is asynchronous for SELF REFRESH exit and for
disabling the outputs. CKE must be maintained HIGH
throughout read and write accesses. Input buffers (excluding
CK, CK# and CKE) are disabled during POWER-DOWN. Input
buffers (excluding CKE) are disabled during SELF REFRESH.
CKE is an SSTL_2 input but will detect an LVCMOS LOW level
after V
DD
is applied and until CKE is first brought HIGH. After
CKE is brought HIGH, it becomes an SSTL_2 input only.
121, 122
S0#, S1#
Input Chip Selects: S# enables (registered LOW) and disables
(registered HIGH) the command decoder. All commands are
masked when S# is registered HIGH. S# is considered part of
the command code.
116, 117
BA0, BA1
Input Bank Address: BA0 and BA1 define to which device bank an
ACTIVE, READ, WRITE, or PRECHARGE command is being
applied.
99
(256MB, 512MB),
100,
A0-A11
(128MB)
Input Address Inputs: Provide the row address for ACTIVE
101, 102, 105, 106, 107, A0-A12
(256MB, 512MB)
commands, and the column address and auto precharge bit
108, 109, 110, 111, 112,
(A10) for READ/WRITE commands, to select one location out
115
of the memory array in the respective device bank. A10
sampled during a PRECHARGE command determines whether
the PRECHARGE applies to one device bank (A10 LOW, device
bank selected by BA0, BA1) or all device banks (A10 HIGH).
The address inputs also provide the op-code during a MODE
REGISTER SET command. BA0 and BA1 define which mode
register (mode register or extended mode register) is loaded
during the LOAD MODE REGISTER command.
11, 25, 47, 61, 133, 147,
DQS0-DQS7
Input/ Data Strobe: Output with READ data, input with WRITE data.
169, 183
Output DQS is edge-aligned with READ data, centered in WRITE data.
Used to capture data.
12, 26, 48, 62, 134, 148,
DM0-DM7
Input Data Write Mask. DM LOW allows WRITE operation. DM HIGH
170, 184
blocks WRITE operation. DM lines do not affect READ
operation.
09005aef806e1d28
DD8C16_32_64x64HDG_B.fm - Rev. B 10/03 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
128MB, 256MB, 512MB (x64)
200-PIN DDR SODIMM
Table 5:
Pin Descriptions
SYMBOL
DQ0-DQ63
TYPE
Input/ Data I/Os: Data bus.
Output
DESCRIPTION
Pin numbers may not correlate with symbols. Refer to Pin Assignment Tables for pin number and symbol information
PIN NUMBERS
5, 6, 7, 8, 13, 14, 17, 18,
19, 20, 23, 20, 29, 30, 31,
32, 41, 42, 43, 44, 49, 50,
53, 54, 55, 56, 59, 60, 65,
66, 67, 67, 127, 128, 129,
130, 135, 136, 139, 140,
141, 142, 145, 146, 151,
152, 153, 154, 163, 164,
165, 166, 171, 172, 175,
176, 177, 178, 181, 182,
187, 188, 189, 190
195
194, 196, 198
193
SCL
SA0-SA2
SDA
1, 2
9, 10, 21, 22, 33, 34, 36,
45, 46, 57, 58, 69, 70, 81,
82, 92, 93, 94, 113, 114,
131, 132, 143, 144, 155,
156, 157, 167, 168, 179,
180, 191, 192
3, 4, 15, 16, 27, 28, 38, 39,
40, 51, 52, 63, 64, 75, 76,
87, 88, 90, 103, 104, 125,
126, 137, 138, 149, 150,
159, 161, 162, 173, 174,
185, 186
197
71, 72, 73, 74, 77, 78, 79,
80, 83, 84
85, 97, 98,
99 (128MB only), 123,
124, 199, 200
V
REF
V
DD
Input Serial Clock for Presence-Detect: SCL is used to synchronize
the presence-detect data transfer to and from the module.
Input Presence-Detect Address Inputs: These pins are used to
configure the presence-detect device.
Input/ Serial Presence-Detect Data: SDA is a bidirectional pin used to
Output transfer addresses and data into and out of the presence-
detect portion of the module.
Input SSTL_2 reference voltage.
Supply Power Supply: +2.5V ±0.2V.
See note 50 on page 23.
V
SS
Supply Ground.
V
DDSPD
DNU
NC
Supply Serial EEPROM positive power supply: +2.3V to +3.6V.
—
Do Not Use: These pins are not connected on these modules,
but are assigned pins on other modules in this product family.
—
No Connect: These pins should be left unconnected.
09005aef806e1d28
DD8C16_32_64x64HDG_B.fm - Rev. B 10/03 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
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