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SST89V54RDA-33-C-PIE

产品描述Microcontroller, 8-Bit, FLASH, 8051 CPU, 33MHz, CMOS, PDIP40, ROHS COMPLIANT, PLASTIC, MS-011AC, DIP-40
产品类别嵌入式处理器和控制器    微控制器和处理器   
文件大小2MB,共84页
制造商Silicon Laboratories Inc
标准
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SST89V54RDA-33-C-PIE概述

Microcontroller, 8-Bit, FLASH, 8051 CPU, 33MHz, CMOS, PDIP40, ROHS COMPLIANT, PLASTIC, MS-011AC, DIP-40

SST89V54RDA-33-C-PIE规格参数

参数名称属性值
是否Rohs认证符合
厂商名称Silicon Laboratories Inc
零件包装代码DIP
包装说明DIP, DIP40,.6
针数40
Reach Compliance Codeunknown
ECCN代码3A991.A.2
Is SamacsysN
具有ADCNO
地址总线宽度16
位大小8
CPU系列8051
最大时钟频率33 MHz
DAC 通道NO
DMA 通道NO
外部数据总线宽度8
JESD-30 代码R-PDIP-T40
JESD-609代码e3
长度51.943 mm
I/O 线路数量32
端子数量40
最高工作温度70 °C
最低工作温度
PWM 通道YES
封装主体材料PLASTIC/EPOXY
封装代码DIP
封装等效代码DIP40,.6
封装形状RECTANGULAR
封装形式IN-LINE
峰值回流温度(摄氏度)260
电源3/3.3 V
认证状态Not Qualified
RAM(字节)1024
ROM(单词)16384
ROM可编程性FLASH
座面最大高度5.588 mm
速度33 MHz
最大压摆率47 mA
最大供电电压3.6 V
最小供电电压2.7 V
标称供电电压3 V
表面贴装NO
技术CMOS
温度等级COMMERCIAL
端子面层MATTE TIN
端子形式THROUGH-HOLE
端子节距2.54 mm
端子位置DUAL
处于峰值回流温度下的最长时间40
宽度15.24 mm
uPs/uCs/外围集成电路类型MICROCONTROLLER
Base Number Matches1

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FlashFlex MCU
SST89E54RD2A/RDA / SST89E58RD2A/RDA
SST89V54RD2A/RDA / SST89V58RD2A/RDA
Data Sheet
FEATURES:
• 8-bit 8051-Compatible Microcontroller (MCU)
with Embedded SuperFlash Memory
– Fully Software Compatible
– Development Toolset Compatible
– Pin-For-Pin Package Compatible
• SST89E5xRD2A Operation
– 0 to 40 MHz at 5V
• SST89V5xRD2A Operation
– 0 to 33 MHz at 3V
• 1 KByte Internal RAM
• Dual Block SuperFlash EEPROM
– 16/32 KByte primary block +
8 KByte secondary block
(128-Byte sector size for both blocks)
– Individual Block Security Lock with SoftLock
– Concurrent Operation during
In-Application Programming (IAP)
– Memory Overlay for Interrupt Support during IAP
• Support External Address Range up to 64
KByte of Program and Data Memory
• Three High-Current Drive Ports (16 mA each)
• Three 16-bit Timers/Counters
• Full-Duplex, Enhanced UART
– Framing Error Detection
– Automatic Address Recognition
• Ten Interrupt Sources at 4 Priority Levels
– Four External Interrupt Inputs
• Programmable Watchdog Timer (WDT)
• Programmable Counter Array (PCA)
• Four 8-bit I/O Ports (32 I/O Pins) and
One 4-bit Port
• Second DPTR register
• Low EMI Mode (Inhibit ALE)
• SPI Serial Interface
• Standard 12 Clocks per cycle, the device has an
option to double the speed to 6 clocks per cycle.
• TTL- and CMOS-Compatible Logic Levels
• Brown-out Detection
• Low Power Modes
– Power-down Mode with External Interrupt Wake-up
– Idle Mode
• Temperature Ranges:
– Commercial (0°C to +70°C)
– Industrial (-40°C to +85°C)
• Packages Available
– 40-contact WQFN (Port 4 feature not available)
– 44-lead PLCC
– 40-pin PDIP (Port 4 feature not available)
– 44-lead TQFP
• All non-Pb (lead-free) devices are RoHS compliant
PRODUCT DESCRIPTION
The SST89E5xRD2A/RDA and SST89V5xRD2A/RDA are
members of the FlashFlex family of 8-bit microcontroller
products designed and manufactured with SST patented
and proprietary SuperFlash CMOS semiconductor pro-
cess technology. The split-gate cell design and thick-oxide
tunneling injector offer significant cost and reliability bene-
fits for SST customers. The devices use the 8051 instruc-
tion set and are pin-for-pin compatible with standard 8051
microcontroller devices.
The devices come with 24/40 KByte of on-chip flash
EEPROM program memory which is partitioned into 2
independent program memory blocks. The primary Block 0
occupies 16/32 KByte of internal program memory space
and the secondary Block 1 occupies 8 KByte of internal
program memory space.
The 8-KByte secondary block can be mapped to the lowest
location of the 16/32 KByte address space; it can also be
hidden from the program counter and used as an indepen-
dent EEPROM-like data memory.
In addition to the 24/40 KByte of EEPROM program mem-
ory on-chip and 1024 x8 bits of on-chip RAM, the devices
can address up to 64 KByte of external program memory
and up to 64 KByte of external RAM.
The flash memory blocks can be programmed via a stan-
dard 87C5x OTP EPROM programmer fitted with a special
adapter and the firmware for SST devices. During power-
on reset, the devices can be configured as either a slave to
an external host for source code storage or a master to an
external host for an in-application programming (IAP) oper-
ation. The devices are designed to be programmed in-sys-
tem and in-application on the printed circuit board for
maximum flexibility. The devices are pre-programmed with
an example of the bootstrap loader in the memory, demon-
strating the initial user program code loading or subsequent
user code updating via the IAP operation. The sample
bootstrap loader is available for the user’s reference and
convenience only; SST does not guarantee its functionality
or usefulness. Chip-Erase or Block-Erase operations will
erase the pre-programmed sample code.
©2007 Silicon Storage Technology, Inc.
S71339-01-000
1/07
1
The SST logo, SuperFlash, and FlashFlex are registered trademarks of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.

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